Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal LFCSP 32 WQ

16-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,

1.8 V Analog-to-Digital Converter

Data Sheet

AD9266

Rev. A

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FEATURES

1.8 V analog supply operation

1.8 V to 3.3 V output supply

SNR

77.6 dBFS at 9.7 MHz input

71.1 dBFS at 200 MHz input

SFDR

93 dBc at 9.7 MHz input

80 dBc at 200 MHz input

Low power

56 mW at 20 MSPS

113 mW at 80 MSPS

Differential input with 700 MHz bandwidth

On-chip voltage reference and sample-and-hold circuit

2 V p-p differential analog input

DNL = −0.6/+1.1 LSB

Interleaved data output for reduced pin-count interface

Serial port control options

Offset binary, Gray code, or twos complement data format

Optional clock duty cycle stabilizer

Integer 1-to-8 input clock divider

Built-in selectable digital test pattern generation

Energy-saving power-down modes

Data clock output (DCO) with programmable clock and

data alignment

APPLICATIONS

Communications

Diversity radio systems

Multimode digital receivers

GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA

Smart antenna systems

Battery-powered instruments

Handheld scope meters

Portable medical imaging

Ultrasound

Radar/LIDAR

PET/SPECT imaging

FUNCTIONAL BLOCK DIAGRAM

VIN+

VIN–

VREF

SENSE

D1_D0

D15_D14

DCO

SDIOAGND DRVDDAVDD SCLK

SPI

PROGRAMMING DATA

VCM

RBIAS

PDWN DFSCLK+ CLK–

MODE

CONTROLS

DUTY CYCLE

STABILIZER

DIVIDE

1 TO 8

MODE

CSB

REF

SELECT

ADC

CORE

CMOS

OUTPUT BUFFER

AD9266

08678-001

Figure 1.

PRODUCT HIGHLIGHTS

1. The AD9266 operates from a single 1.8 V analog power

supply and features a separate digital output driver supply

to accommodate 1.8 V to 3.3 V logic families.

2. The patented sample-and-hold circuit maintains excellent

performance for input frequencies up to 200 MHz and is

designed for low cost, low power, and ease of use.

3. A standard serial port interface supports various product

features and functions, such as data output formatting,

internal clock divider, power-down, DCO and data output

(D15_D14 to D1_D0) timing and offset adjustments, and

voltage reference modes.

4. The AD9266 is packaged in a 32-lead RoHS-compliant

LFCSP that is pin compatible with the AD9609 10-bit

ADC, the AD9629 12-bit ADC, and the AD9649 14-bit

ADC, enabling a simple migration path between 10-bit and

16-bit converters sampling from 20 MSPS to 80 MSPS.

Summary of content (32 pages)

PAGE 1
6-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter AD9266 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR 77.6 dBFS at 9.7 MHz input 71.1 dBFS at 200 MHz input SFDR 93 dBc at 9.7 MHz input 80 dBc at 200 MHz input Low power 56 mW at 20 MSPS 113 mW at 80 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = −0.6/+1.
PAGE 2
AD9266 Data Sheet TABLE OF CONTENTS ‘Features ............................................................................................. 1 Voltage Reference ....................................................................... 19 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 20 Functional Block Diagram ..........................................................
PAGE 3
Data Sheet AD9266 GENERAL DESCRIPTION The AD9266 is a monolithic, single-channel 1.8 V supply, 16-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-andhold circuit and on-chip voltage reference. A differential clock input with a selectable internal 1-to-8 divide ratio controls all internal conversion cycles.
PAGE 4
AD9266 Data Sheet SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error 1 Differential Nonlinearity (DNL) 2 Integral Nonlinearity (INL)2 TEMPERATURE DRIFT Offset Error INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Load Regulation Error at 1.
PAGE 5
Data Sheet AD9266 AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz fIN = 30.
PAGE 6
AD9266 Data Sheet DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 3.
PAGE 7
Data Sheet AD9266 SWITCHING SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 4.
PAGE 8
AD9266 Data Sheet TIMING SPECIFICATIONS Table 5.
PAGE 9
Data Sheet AD9266 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter AVDD to AGND DRVDD to AGND VIN+, VIN− to AGND CLK+, CLK− to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/PDWN to AGND MODE/OR to AGND D1_D0 Through D15_D14 to AGND DCO to AGND Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) Rating −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.
PAGE 10
AD9266 Data Sheet 32 31 30 29 28 27 26 25 AVDD VIN+ VIN– AVDD RBIAS VCM SENSE VREF PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 AD9266 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 AVDD MODE/OR DCO (MSB) D15_D14 D13_D12 D11_D10 D9_D8 D7_D6 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE (PIN 0) IS THE ONLY GND CONNECTION ON THE CHIP AND MUST BE CONNECTED TO THE PCB AGND.
PAGE 11
Data Sheet AD9266 TYPICAL PERFORMANCE CHARACTERISTICS AD9266-80 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 0 0 80MSPS 9.7MHz @ –1dBFS SNR = 76.8dB (77.8dBFS) SFDR = 94.3dBc –40 –60 –80 –100 –60 –80 –100 –120 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) –140 08678-033 –140 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) Figure 4.
PAGE 12
AD9266 Data Sheet AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 100 1.5 SFDR (dBc) 90 1.0 70 SNR (dBFS) DNL ERROR (LSB) SNR/SFDR (dBFS/dBc) 80 60 50 40 30 20 0.5 0 –0.5 –1.0 0 50 100 150 INPUT FREQUENCY (MHz) 200 –1.5 08678-057 0 0 Figure 10. AD9266-80 SNR/SFDR vs.
PAGE 13
Data Sheet AD9266 AD9266-65 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 120 0 65MSPS 9.7MHz @ –1dBFS SNR = 76.9dB (77.9dBFS) SFDR = 95.9dBc SFDRFS 100 –40 SNR/SFDR (dBFS/dBc) –60 –80 –100 SNRFS SFDR 60 SNR 40 20 –120 0 5 10 15 20 25 30 FREQUENCY (MHz) 0 –65 –60 08678-030 –140 –50 –40 –30 –20 INPUT AMPLITUDE (dBFS) –10 0 Figure 19.
PAGE 14
AD9266 Data Sheet AD9266-40 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 120 0 40MSPS 9.7MHz @ –1dBFS SNR = 76.9dB (77.9dBFS) SFDR = 95.1dBc SFDRFS 100 –40 SNR/SFDR (dBFS/dBc) –60 –80 –100 SNRFS SFDR 60 SNR 40 20 –120 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz) 0 –65 –60 08678-028 –140 0 40MSPS 30.6MHz @ –1dBFS SNR = 76.6dB (77.6dBFS) SFDR = 88.
PAGE 15
Data Sheet AD9266 AD9266-20 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 0 120 20MSPS 9.7MHz @ –1dBFS SNR = 76.9dB (77.9dBFS) SFDR = 95.6dBc SFDRFS 100 –40 SNR/SFDR (dBFS/dBc) –60 –80 –100 60 SFDR (dBc) 40 SNR (dBc) 20 –120 0 1 2 3 4 5 6 7 8 9 10 FREQUENCY (MHz) 0 –90 08678-024 –140 Figure 24. AD9266-20 Single-Tone FFT with fIN = 9.
PAGE 16
AD9266 Data Sheet EQUIVALENT CIRCUITS DRVDD AVDD VIN± 08678-042 08678-039 D1_D0 TO D15_D14, OR Figure 27. Equivalent Analog Input Circuit Figure 31. Equivalent D1_D0 to D15_D14 and OR Digital Output Circuit DRVDD AVDD SCLK/DFS, MODE, SDIO/PDWN 30kΩ 08678-047 7.5kΩ 350Ω 08678-043 375Ω VREF Figure 32. Equivalent SCLK/DFS, MODE, and SDIO/PDWN Input Circuit Figure 28. Equivalent VREF Circuit AVDD DRVDD AVDD 375Ω CSB 30kΩ 350Ω 08678-045 08678-046 SENSE Figure 29.
PAGE 17
Data Sheet AD9266 THEORY OF OPERATION Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors.
PAGE 18
AD9266 Data Sheet In any configuration, the value of Shunt Capacitor C is dependent on the input frequency and source impedance and may need to be reduced or removed. Table 9 displays the suggested values to set the RC network. However, these values are dependent on the input signal and should be used only as a starting guide. For baseband applications below ~10 MHz where SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 38.
PAGE 19
Data Sheet AD9266 VOLTAGE REFERENCE Internal Reference Connection A comparator within the AD9266 detects the potential at the SENSE pin and configures the reference into two possible modes, which are summarized in Table 10. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 42), setting VREF to 1.0 V. –0.5 –1.0 INTERNAL VREF = 0.995V –1.5 –2.0 –2.5 –3.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 2.0 1.
PAGE 20
AD9266 Data Sheet CLOCK INPUT CONSIDERATIONS For optimum performance, clock the AD9266 sample clock inputs, CLK+ and CLK−, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 45) and require no external bias. AVDD CLK– 2pF 08678-016 0.1µF 0.1µF CLOCK INPUT CLK+ Clock Input Options 0.1µF The AD9266 has a very flexible clock input structure.
PAGE 21
Data Sheet AD9266 Input Clock Divider Jitter Considerations The AD9266 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. Optimum performance can be obtained by enabling the internal duty cycle stabilizer (DCS) when using divide ratios other than 1, 2, or 4. High speed, high resolution ADCs are sensitive to the quality of the clock input.
PAGE 22
AD9266 Data Sheet POWER DISSIPATION AND STANDBY MODE As shown in Figure 53, the analog core power dissipated by the AD9266 is proportional to its sample rate. The digital power dissipation of the CMOS outputs are determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current (IDRVDD) can be calculated as IDRVDD = VDRVDD × CLOAD × fCLK × N where N is the number of output bits (nine, in the case of the AD9266).
PAGE 23
Data Sheet AD9266 TIMING The AD9266 provides latched data with a pipeline delay of eight clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Minimize the length of the output data lines and loads placed on them to reduce transients within the AD9266. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD9266 is 3 MSPS. At clock rates below 3 MSPS, dynamic performance may degrade.
PAGE 24
AD9266 Data Sheet OUTPUT TEST The AD9266 includes various output test options to place predictable values on the outputs of the AD9266. OUTPUT TEST MODES The output test options are described in Table 16 at Address 0x0D. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back end blocks and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not.
PAGE 25
Data Sheet AD9266 SERIAL PORT INTERFACE (SPI) The AD9266 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port.
PAGE 26
AD9266 Data Sheet HARDWARE INTERFACE The pins described in Table 13 constitute the physical interface between the programming device of the user and the serial port of the AD9266. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers.
PAGE 27
Data Sheet AD9266 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE DEFAULT VALUES Each row in the memory map register table (see Table 16) contains eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the device index and transfer register (Address 0xFF); the program registers, including setup, control, and test (Address 0x08 to Address 0x2A); and the AD9266-specific customer SPI control register (Address 0x101).
PAGE 28
AD9266 Data Sheet MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 16 are not currently supported for this device. Table 16.
PAGE 29
Data Sheet AD9266 Addr (Hex) 0x15 Register Name Output adjust 0x16 Output phase DCO output polarity 0 = normal 1 = inverted 0x17 Output delay Enable DCO delay Open Enable data delay 0x19 USER_PATT1_LSB B7 B6 B5 B4 0x1A USER_PATT1_MSB B15 B14 B13 0x1B USER_PATT2_LSB B7 B6 0x1C USER_PATT2_MSB B15 B14 0x2A OR/MODE select Bit 7 (MSB) Bit 6 3.
PAGE 30
AD9266 Data Sheet MEMORY MAP REGISTER DESCRIPTIONS Bit 2—Run GCLK For additional information about functions that are controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI at www.analog.com. This bit enables the GCLK oscillator. For some applications with encode rates below 10 MSPS, it may be preferable to set this bit high to supersede the GCLK detector.
PAGE 31
Data Sheet AD9266 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9266 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and Ground Recommendations When connecting power to the AD9266, it is strongly recommended that two separate supplies be used. Use one 1.8 V supply for analog (AVDD); use a separate 1.8 V to 3.
PAGE 32
AD9266 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 1 24 0.50 BSC *3.75 3.60 SQ 3.55 EXPOSED PAD 17 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5 WITH EXCEPTION TO EXPOSED PAD DIMENSION.