Datasheet

AD9260
Rev. C | Page 33 of 44
POWER DISSIPATION CONSIDERATIONS
The power dissipation of the AD9260 is dependent on its
application specific configuration and operating conditions.
The analog power dissipation as shown in Figure 70 is primarily
a function of its power bias setting and sample rate. It remains
insensitive to the particular input waveform being digitized or
digital filter MODE setting. The digital power dissipation is
primarily a function of the digital supply setting (i.e., +3 V to
+5 V), the sample rate and, to a lesser extent, the MODE setting
and input waveform. Figure 71 and Figure 72 show the total
current dissipation of the combined digital (DVDD) and digital
driver supply (DRVDD) for +3 V and +5 V supplies. Note,
DVDD and DRVDD are typically derived from the same supply
bus since no degradation in performance results. A 1 MHz full-
scale sine wave was used to ensure maximum digital activity in
the digital filters and the digital drivers had a fanout of one.
Note also that a twofold decrease in digital supply current
results when the digital supply is reduced form +5 V to +3 V.
30
50
70
90
110
130
I
AVDD
(mA)
SAMPLE RATE (MSPS)
51510 20
00581-C-070
QUARTER BIAS [8k Ω ]
FULL BIAS [2k
Ω ]
HALF BIAS [4k
Ω ]
Figure 70. I
AVDD
vs. Sample Rate (AVDD = +5V, Mode 1x-4x)
0
2
4
6
8
10
I
DVDD
/I
DRVDD
(mA)
12
14
16
SAMPLE RATE (MSPS)
51510 20
00581-C-071
8 × MODE
4
× MODE
2
× MODE
1
× MODE
Figure 71. IDVDD/IDRVDD vs. Sample Rate (DVDD = DRVDD = 3 V,
f
IN
= 1 MHz)
0
5
10
15
20
25
30
I
DVDD
/I
DRVDD
(mA)
SAMPLE RATE (MSPS)
51510 20
00581-C-072
8 × MODE
4 × MODE
2
× MODE
1
× MODE
Figure 72. I
DVDD
/I
DRVDD
vs. Sample Rate (DVDD = DRVDD = 5 V, f
IN
= 1
MHz)
DIGITAL OUTPUT DRIVER CONSIDERATIONS
(DRVDD)
The AD9260 output drivers can be configured to interface with
+5 V or 3.3 V logic families by setting DRVDD to +5 V or 3.3 V,
respectively. The AD9260 output drivers in each mode are
appropriately sized to provide sufficient output current to drive
a wide variety of logic families. However, large drive currents
tend to cause glitches on the supplies and may affect SINAD
performance. Applications requiring the AD9260 to drive large
capacitive loads or large fanout may require additional
decoupling capacitors on DRVDD. The addition of external
buffers or latches helps reduce output loading while providing
effective isolation from the data bus.
Clock Input and Considerations
The AD9260 internal timing uses the two edges of the clock
input to generate a variety of internal timing signals. The clock
input must meet or exceed the minimum specified pulse width
high and low (t
CH
and t
CL
) specifications for the given A/D as
defined in the Switching Specifications at the beginning of the
data sheet to meet the rated performance specifications. For
example, the clock input to the AD9260 operating at 20 MSPS
may have a duty cycle between 45% and 55% to meet this
timing requirement since the minimum specified t
CH
and t
CL
is
22.5 ns. For clock rates below 20 MSPS, the duty cycle may
deviate from this range to the extent that both t
CH
and t
CL
are
satisfied. All high speed, high resolution A/Ds are sensitive to
the quality of the clock input. The degradation in SNR at a
given full-scale input frequency (f
IN
) due to only aperture jitter
(t
A
) can be calculated with the following equation:
(
)
[
]
A
IN
tfSNR π= 2/1log20
10
In the equation, the rms aperture jitter, t
A
, represents the
rootsum square of all the jitter sources which include the clock
input, analog input signal, and A/D aperture jitter specification.
For example, if a 500 kHz full-scale sine wave is sampled by an