Datasheet

AD9258
Rev. A | Page 9 of 44
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless
otherwise noted.
Table 4.
AD9258BCPZ-80 AD9258BCPZ-105 AD9258BCPZ-125
Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit
CLOCK INPUT PARAMETERS
Input Clock Rate Full 625 625 625 MHz
Conversion Rate
1
DCS Enabled Full 20 80 20 105 20 125 MSPS
DCS Disabled Full 10 80 10 105 10 125 MSPS
CLK Period—Divide-by-1 Mode (t
CLK
) Full 12.5 9.5 8 ns
CLK Pulse Width High (t
CH
)
Divide-by-1 Mode, DCS Enabled Full
3.75
6.25
8.75 2.85
4.75
6.65
2.4 4 5.6 ns
Divide-by-1 Mode, DCS Disabled Full
5.95
6.25
6.55 4.5
4.75
5.0
3.8 4 4.2 ns
Divide-by-2 Mode Through
Divide-by-8 Mode
Full 0.8
0.8 0.8 ns
Aperture Delay (t
A
) Full 1.0 1.0 1.0 ns
Aperture Uncertainty (Jitter, t
J
) Full 0.07 0.07 0.07
ps
rms
DATA OUTPUT PARAMETERS
CMOS Mode
Data Propagation Delay (t
PD
) Full 2.8 3.5
4.2 2.8
3.5 4.2 2.8 3.5 4.2 ns
DCO Propagation Delay (t
DCO
)
2
Full 3.1 3.1 3.1 ns
DCO to Data Skew (t
SKEW
) Full −0.6 −0.4 0 −0.6 −0.4 0 −0.6 −0.4 0 ns
LVDS Mode
Data Propagation Delay (t
PD
Full 2.9 3.7 4.5 2.9 3.7 4.5 2.9 3.7 4.5 ns
DCO Propagation Delay (t
DCO
)
2
Full 3.9 3.9 3.9 ns
DCO to Data Skew (t
SKEW
) Full −0.1 +0.2 +0.5 −0.1 +0.2 +0.5 −0.1 +0.2 +0.5 ns
CMOS Mode Pipeline Delay
(Latency)
Full 12 12 12 Cycles
LVDS Mode Pipeline Delay
(Latency) Channel A/Channel B
Full 12/12.5 12/12.5 12/12.5 Cycles
Wake-Up Time
3
Full 500 500 500 μs
Out-of-Range Recovery Time Full 2 2 2 Cycles
1
Conversion rate is the clock rate after the divider.
2
Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17).
3
Wake-up time is defined as the time required to return to normal operation from power-down mode.