Datasheet

AD9258
Rev. A | Page 7 of 44
AD9258BCPZ-80 AD9258BCPZ-105 AD9258BCPZ-125
Parameter
1
Temp Min Typ Max Min Typ Max Min Typ Max Unit
WORST OTHER (HARMONIC OR SPUR)
Without Dither
f
IN
= 2.4 MHz 25°C −100 −100 −99 dBc
f
IN
= 70 MHz 25°C −100 −96 −99 −94 −98 −94 dBc
Full −96 −94 −94 dBc
f
IN
= 140 MHz 25°C −97 −97 −97 dBc
f
IN
= 200 MHz 25°C −95 −95 −95 dBc
With On-Chip Dither
f
IN
= 2.4 MHz 25°C −109 −107 −107 dBc
f
IN
= 70 MHz 25°C −105 −96 −106 −95 −105 −95 dBc
Full −96 −95 −95 dBc
f
IN
= 140 MHz 25°C −106 −104 −103 dBc
f
IN
= 200 MHz 25°C −102 −104 −97 dBc
TWO-TONE SFDR WITHOUT DITHER
f
IN
= 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS ) 25°C 93 92 90 dBc
f
IN
= 169 MHz (−7 dBFS ),172 MHz (−7 dBFS ) 25°C 81 80 82 dBc
CROSSTALK
2
Full −95 −95 −95 dB
ANALOG INPUT BANDWIDTH 25°C 650 650 650 MHz
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2
Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless
otherwise noted.
Table 3.
Parameter Temperature Min Typ Max Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Internal Common-Mode Bias Full 0.9 V
Differential Input Voltage Full 0.3 3.6 V p-p
Input Voltage Range Full AGND AVDD V
Input Common-Mode Range Full 0.9 1.4 V
High Level Input Current Full −100 +100 μA
Low Level Input Current Full −100 +100 μA
Input Capacitance Full 4 pF
Input Resistance Full 8 10 12 kΩ
SYNC INPUT
Logic Compliance CMOS
Internal Bias Full 0.9 V
Input Voltage Range Full AGND AVDD V
High Level Input Voltage Full 1.2 AVDD V
Low Level Input Voltage Full AGND 0.6 V
High Level Input Current Full −100 +100 μA
Low Level Input Current Full −100 +100 μA
Input Capacitance Full 1 pF
Input Resistance Full 12 16 20 kΩ