Datasheet

AD9258
Rev. A | Page 16 of 44
Pin No. Mnemonic Type Description
16 D3+ Output Channel A/Channel B LVDS Output Data 3—True.
15 D3− Output Channel A/Channel B LVDS Output Data 3—Complement.
18 D4+ Output Channel A/Channel B LVDS Output Data 4 —True.
17 D4− Output Channel A/Channel B LVDS Output Data 4—Complement.
21 D5+ Output Channel A/Channel B LVDS Output Data 5—True.
20 D5− Output Channel A/Channel B LVDS Output Data 5—Complement.
23 D6+ Output Channel A/Channel B LVDS Output Data 6—True.
22 D6− Output Channel A/Channel B LVDS Output Data 6—Complement.
27 D7+ Output Channel A/Channel B LVDS Output Data 7—True.
26 D7− Output Channel A/Channel B LVDS Output Data 7—Complement.
30 D8+ Output Channel A/Channel B LVDS Output Data 8—True.
29 D8− Output Channel A/Channel B LVDS Output Data 8—Complement.
32 D9+ Output Channel A/Channel B LVDS Output Data 9—True.
31 D9− Output Channel A/Channel B LVDS Output Data 9—Complement.
34 D10+ Output Channel A/Channel B LVDS Output Data 10—True.
33 D10− Output Channel A/Channel B LVDS Output Data 10—Complement.
36 D11+ Output Channel A/Channel B LVDS Output Data 11—True.
35 D11− Output Channel A/Channel B LVDS Output Data 11—Complement.
39 D12+ Output Channel A/Channel B LVDS Output Data 12—True.
38 D12− Output Channel A/Channel B LVDS Output Data 12—Complement.
41 D13+ (MSB) Output Channel A/Channel B LVDS Output Data 13—True.
40 D13− (MSB) Output Channel A/Channel B LVDS Output Data 13—Complement.
43 OR+ Output Channel A/Channel B LVDS Overrange Output—True.
42 OR− Output Channel A/Channel B LVDS Overrange Output—Complement.
25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True.
24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement.
SPI Control
45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode.
44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
46 CSB Input SPI Chip Select (Active Low).
ADC Configuration
47 OEB Input Output Enable Input (Active Low) in External Pin Mode.
48 PDWN Input
Power-Down Input in External Pin Mode. In SPI mode, this input can be configured
as power-down or standby.