Datasheet

AD9258
Rev. A | Page 14 of 44
Pin No. Mnemonic Type Description
32 D4A Output Channel A CMOS Output Data.
33 D5A Output Channel A CMOS Output Data.
34 D6A Output Channel A CMOS Output Data.
35 D7A Output Channel A CMOS Output Data.
36 D8A Output Channel A CMOS Output Data.
38 D9A Output Channel A CMOS Output Data.
39 D10A Output Channel A CMOS Output Data.
40 D11A Output Channel A CMOS Output Data.
41 D12A Output Channel A CMOS Output Data.
42 D13A (MSB) Output Channel A CMOS Output Data.
43 ORA Output Channel A Overrange Output.
6 D0B (LSB) Output Channel B CMOS Output Data.
7 D1B Output Channel B CMOS Output Data.
8 D2B Output Channel B CMOS Output Data.
9 D3B Output Channel B CMOS Output Data.
11 D4B Output Channel B CMOS Output Data.
12 D5B Output Channel B CMOS Output Data.
13 D6B Output Channel B CMOS Output Data.
14 D7B Output Channel B CMOS Output Data.
15 D8B Output Channel B CMOS Output Data.
16 D9B Output Channel B CMOS Output Data.
17 D10B Output Channel B CMOS Output Data.
18 D11B Output Channel B CMOS Output Data.
20 D12B Output Channel B CMOS Output Data.
21 D13B (MSB) Output Channel B CMOS Output Data.
22 ORB Output Channel B Overrange Output
24 DCOA Output Channel A Data Clock Output.
23 DCOB Output Channel B Data Clock Output.
SPI Control
45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode.
44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
46 CSB Input SPI Chip Select (Active Low).
ADC Configuration
47 OEB Input Output Enable Input (Active Low) in External Pin Mode.
48 PDWN Input
Power-Down Input in External Pin Mode. In SPI mode, this input can be
configured as power-down or standby.