Datasheet

AD9258
Rev. A | Page 10 of 44
TIMING SPECIFICATIONS
Table 5.
Parameter Conditions Limit
SYNC TIMING REQUIREMENTS
t
SSYNC
SYNC to rising edge of CLK+ setup time 0.30 ns typ
t
HSYNC
SYNC to rising edge of CLK+ hold time 0.40 ns typ
SPI TIMING REQUIREMENTS
t
DS
Setup time between the data and the rising edge of SCLK 2 ns min
t
DH
Hold time between the data and the rising edge of SCLK 2 ns min
t
CLK
Period of the SCLK 40 ns min
t
S
Setup time between CSB and SCLK 2 ns min
t
H
Hold time between CSB and SCLK 2 ns min
t
HIGH
SCLK pulse width high 10 ns min
t
LOW
SCLK pulse width low 10 ns min
t
EN_SDIO
Time required for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge
10 ns min
t
DIS_SDIO
Time required for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge
10 ns min
Timing Diagrams
t
PD
t
SKEW
t
CH
t
DCO
t
CLK
N – 12N – 13
N – 1
N + 1
N + 2
N + 3
N + 5
N + 4
N
N – 11 N – 10 N – 9 N – 8
VIN
CLK+
CLK–
CH A/CH B DATA
DCOA/DCOB
t
A
08124-002
Figure 2. CMOS Default Output Mode Data Output Timing
t
PD
t
SKEW
t
CH
t
DCO
t
CLK
CH A
N – 12
CH B
N – 12
CH A
N – 11
CH B
N – 11
CH A
N – 10
CH B
N – 10
CH A
N – 9
CH B
N – 9
CH A
N – 8
N – 1
N + 1
N + 2
N + 3
N + 5
N + 4
N
VIN
CLK+
CLK–
CH A/CH B DATA
DCOA/DCOB
t
A
08124-057
Figure 3. CMOS Interleaved Output Mode Data Output Timing