Datasheet

Data Sheet AD9257
Rev. A | Page 5 of 40
Parameter
1
Temp
AD9257-40 AD9257-65
Unit Min Typ Max Min Typ Max
CROSSTALK
2
25°C −100 −98 dB
Crosstalk (Overrange Condition)
3
25°C −92 −94 dB
POWER SUPPLY REJECTION RATIO (PSRR)
4
25°C
AVDD 52 52 dB
DRVDD 73 71 dB
ANALOG INPUT BANDWIDTH, FULL POWER
25°C
650
650
MHz
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2
Crosstalk is measured at 10 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel.
3
Overrange condition is 3 dB above the full-scale input range.
4
PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the
amplitudes of the spur voltage over the pin voltage, expressed in decibels.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 3.
Parameter
1
Temp
Min Typ Max
Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Differential Input Voltage
2
Full 0.2 3.6 V p-p
Input Voltage Range Full AGND − 0.2 AVDD + 0.2 V
Input Common-Mode Voltage Full 0.9 V
Input Resistance (Differential) 25°C 15 kΩ
Input Capacitance 25°C 4 pF
LOGIC INPUTS (PDWN, SYNC, SCLK)
Logic 1 Voltage Full 1.2 AVDD + 0.2 V
Logic 0 Voltage Full 0 0.8 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 2 pF
LOGIC INPUT (CSB)
Logic 1 Voltage
Full
1.2
AVDD + 0.2
V
Logic 0 Voltage Full 0 0.8 V
Input Resistance 25°C 26 kΩ
Input Capacitance 25°C 2 pF
LOGIC INPUT (SDIO)
Logic 1 Voltage Full 1.2 AVDD + 0.2 V
Logic 0 Voltage Full 0 0.8 V
Input Resistance 25°C 26 kΩ
Input Capacitance
25°C
5
pF
LOGIC OUTPUT (SDIO)
3
Logic 1 Voltage (I
OH
= 800 μA) Full 1.79 V
Logic 0 Voltage (I
OL
= 50 μA) Full 0.05 V
DIGITAL OUTPUTS (D± x), ANSI-644
Logic Compliance LVDS
Differential Output Voltage (V
OD
) Full 247 350 454 mV
Output Offset Voltage (V
OS
) Full 1.13 1.21 1.38 V
Output Coding (Default) Twos complement
DIGITAL OUTPUTS (D± x), LOW POWER, REDUCED SIGNAL OPTION
Logic Compliance LVDS
Differential Output Voltage (V
OD
) Full 150 200 250 mV
Output Offset Voltage (V
OS
)
Full
1.13
1.21
1.38
V
Output Coding (Default)
Twos complement
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2
This is specified for LVDS and LVPECL only.
3
This is specified for 13 SDIO/DFS pins sharing the same connection.