Datasheet

AD9255 Data Sheet
Rev. C | Page 8 of 44
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS dierential input, 1.0 V internal reference, and
DCS enabled, unless otherwise noted.
Table 4.
AD9255BCPZ-80
1
AD9255BCPZ-105
1
AD9255BCPZ-125
1
Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit
CLOCK INPUT PARAMETERS
Input Clock Rate Full 625 625 625 MHz
Conversion Rate
2
DCS Enabled Full 20 80 20 105 20 125 MSPS
DCS Disabled Full 10 80 10 105 10 125 MSPS
CLK Period—Divide-by-1 Mode (t
CLK
) Full 12.5 9.5 8 ns
CLK Pulse Width High (t
CH
)
Divide-by-1 Mode
DCS Enabled Full 3.75 6.25 8.75 2.85 4.75 6.65 2.4 4 5.6 ns
DCS Disabled 5.9 6.25 6.6 4.5 4.75 5.0 3.8 4 4.2 ns
Divide-by-3 Mode, Divide-by-5 Mode, and
Divide-by-7 Mode, DCS Enabled
3
Full 0.8 0.8 0.8 ns
Divide-by-2 Mode, Divide-by-4 Mode, Divide-
by-6 Mode, and Divide-by-8 Mode, DCS
Enabled or DCS Disabled
3
Full 0.8 0.8 0.8 ns
Aperture Delay (t
A
) Full 1.0 1.0 1.0 ns
Aperture Uncertainty (Jitter, t
J
) Full 0.07 0.07 0.07 ps rms
DATA OUTPUT PARAMETERS
CMOS Mode
Data Propagation Delay (t
PD
) Full 2.4 2.8 3.4 2.4 2.8 3.4 2.4 2.8 3.4 ns
DCO Propagation Delay (t
DCO
)
4
Full 2.7 3.4 4.2 2.7 3.4 4.2 2.7 3.4 4.2 ns
DCO to Data Skew (t
SKEW
) Full 0.3 0.6 0.9 0.3 0.6 0.9 0.3 0.6 0.9 ns
Pipeline Delay (Latency) Full 12 12 12 Cycles
LVDS Mode
Data Propagation Delay (t
PD
) Full 2.6 3.4 4.2 2.6 3.4 4.2 2.6 3.4 4.2 ns
DCO Propagation Delay (t
DCO
)
4
Full 3.3 3.8 4.3 3.3 3.8 4.3 3.3 3.8 4.3 ns
DCO to Data Skew (t
SKEW
) −0.3 +0.4 +1.2 −0.3 +0.4 +1.2 −0.3 +0.4 +1.2
Pipeline Delay (Latency) Full 12.5 12.5 12.5 Cycles
Wake-Up Time
5
Full 500 500 500 μs
OUT-OF-RANGE RECOVERY TIME Full 2 2 2 Cycles
1
The suffix following the part number refers to the model found in the Ordering Guide section.
2
Conversion rate is the clock rate after the divider.
3
See the Input Clock Divider section for additional information on using the DCS with the input clock divider.
4
Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17).
5
Wake-up time is defined as the time required to return to normal operation from power-down mode.