Datasheet

AD9255 Data Sheet
Rev. C | Page 4 of 44
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS dierential input, 1.0 V internal reference, DCS
enabled, unless otherwise noted.
Table 1.
Parameter Temp
AD9255BCPZ-80
1
AD9255BCPZ-105
1
AD9255BCPZ-125
1
Unit
Min Typ Max Min Typ Max Min Typ Max
RESOLUTION Full 14 14 14 Bits
ACCURACY
No Missing Codes Full Guaranteed Guaranteed Guaranteed
Offset Error Full ±0.05 ±0.25 ±0.05 ±0.25 ±0.05 ±0.25 % FSR
Gain Error Full ±0.2 ±2.5 ±0.2 ±2.5 ±0.4 ±2.5 % FSR
Differential Nonlinearity (DNL)
2
Full ±0.4 ±0.4 ±0.45 LSB
25°C ±0.2 ±0.2 ±0.25 LSB
Integral Nonlinearity (INL)
2
Full ±0.9 ±0.9 ±1.2 LSB
25°C ±0.35 ±0.45 ±0.7 LSB
TEMPERATURE DRIFT
Offset Error Full ±2 ±2 ±2 ppm/°C
Gain Error Full ±15 ±15 ±15 ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode) Full +8 ±12 +8 ±12 +8 ±12 mV
Load Regulation at 1.0 mA Full 3 3 3 mV
INPUT REFERRED NOISE
VREF = 1.0 V 25°C 0.62 0.63 0.61 LSB rms
ANALOG INPUT
Input Span, VREF = 1.0 V Full
22
2 V p-p
Input Capacitance
3
Full
88
8 pF
Input Common-Mode Voltage Full
0.9 0.9
0.9 V
REFERENCE INPUT RESISTANCE Full
66
6 kΩ
POWER SUPPLIES
Supply Voltage
AVDD Full
1.7 1.8 1.9 1.7 1.8 1.9
1.7 1.8 1.9 V
DRVDD Full
1.7 1.8 1.9 1.7 1.8 1.9
1.7 1.8 1.9 V
SVDD Full
1.7 3.5 1.7 3.5 1.7 3.5
V
Supply Current
IAVDD
2
Full
126 131 169 176
194 202 mA
IDRVDD
2
(1.8 V CMOS) Full
13 19
23 mA
IDRVDD
2
(1.8 V LVDS) Full
39 42
44 mA
POWER CONSUMPTION
DC Input Full
239 248 321 332
371 382 mW
Sine Wave Input
2
CMOS Output Mode Full
252 338
391 mW
LVDS Output Mode Full
306 384
437 mW
Standby Power
4
Full
54 54
54 mW
Power-Down Power Full
0.05 0.15 0.05 0.15
0.05 0.15 mW
1
The suffix following the part number refers to the model found in the Ordering Guide section.
2
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
4
Standby power is measured with a dc input, the CLK pins (CLK+, CLK−) inactive (set to AVDD or AGND).