Datasheet

AD9255 Data Sheet
Rev. C | Page 38 of 44
Addr.
(Hex)
Register
Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Default
Value
(Hex)
Default Notes/
Comments
0x14 Output
mode
Drive
strength
Output
type
Open Output
enable
bar
Open Output
invert
Output
format
0x00 Configures the
outputs and
the format of
the data
0 = ANSI
LVDS
0 =
CMOS
00 = offset
binary
1 = reduced
LVDS
1 = LVDS 01 = twos
complement
01 = gray code
11 = offset binary
0x16 Clock phase
control
Invert DCO
clock
Open Open Open Open Input clock divider phase adjust 0x00 Allows
selection of
clock delays
into the input
clock divider
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
0x17 DCO output
delay
Open Open Open DCO clock delay 0x00
(delay = 2500 ps × register value/31)
00000 = 0 ps
00001 = 81 ps
00010 = 161 ps
…
11110 = 2419 ps
11111 = 2500 ps
0x18 VREF select Reference voltage
selection
Open Open Open Open Open Open 0xC0
00 = 1.25 V p-p
01 = 1.5 V p-p
10 = 1.75 V p-p
11 = 2.0 V p-p (default)
0x24 BIST
signature LSB
BIST Signature[7:0] 0x00 Read only
0x25 BIST
signature
MSB
BIST Signature[15:8] 0x00 Read only
0x30 Dither
enable
Open Open Open Dither
enable
Open Open Open Open 0x00
Digital Feature Control Register
0x100 Sync control Open Open Open Open Open Clock
divider
next sync
only
Clock
divider
sync
enable
Master
sync
enable
0x00