Datasheet

Data Sheet AD9255
Rev. C | Page 35 of 44
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin and the SCLK/DFS pin serve as standalone
CMOS-compatible control pins. When the device is powered
up, it is assumed that the user intends to use the pins as static
control lines for the duty cycle stabilizer and output data format
feature control. In this mode, connect the CSB chip select to
AVDD, which disables the serial port interface.
The OEB pin, the DITHER pin, the LVDS pin, the LVDS_RS
pin, and the PDWN pin are active control lines in both external
pin mode and SPI mode. The input from these pins or the SPI
register setting (the logical OR of the SPI bit and the pin function)
is used to determine the mode of operation for the part.
Table 15. Mode Selection
Pin
External
Voltage
Configuration
SDIO/DCS SVDD (default) Duty cycle stabilizer enabled
AGND
Duty cycle stabilizer disabled
SCLK/DFS SVDD Twos complement enabled
AGND (default) Offset binary enabled
OEB DRVDD Outputs in high impedance
AGND (default) Outputs enabled
PDWN AVDD
Chip in power-down or
standby mode
AGND (default) Normal operation
LVDS AGND (default) CMOS output mode
AVDD LVDS output mode
LVDS_RS AGND (default) ANSI LVDS output levels
AVDD
Reduced swing LVDS
output levels
DITHER AGND (default) Dither disabled
AVDD Dither enabled
SPI ACCESSIBLE FEATURES
Table 16 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in AN-877 Application Note, Interfacing to High Speed ADCs via
SPI. The AD9255 part-specific features are described in detail
following Table 17, the external memory map register table.
Table 16. Features Accessible Using the SPI
Feature Name Description
Mode
Allows the user to set either power-down mode
or standby mode
Clock
Allows the user to access the DCS, set the
clock divider, set the clock divider phase, and
enable the SYNC input
Offset
Allows the user to digitally adjust the
converter offset
Test I/O
Allows the user to set test modes to have
known data on output bits
Output Mode Allows the user to set the output mode
Output Phase Allows the user to set the output clock polarity
Output Delay Allows the user to vary the DCO delay
VREF Allows the user to set the reference voltage
DON’T CARE
DON’T CAREDON’T CARE
DON’T CARE
SDIO
SCLK
CSB
t
S
t
DH
t
CLK
t
DS
t
H
R/W W1 W0 A12 A11 A10 A9 A8 A7
D5 D4 D3 D2 D1 D0
t
LOW
t
HIGH
08505-055
Figure 84. Serial Port Interface Timing Diagram