Datasheet
Data Sheet AD9255
Rev. C | Page 13 of 44
13
14
15
16
17
18
19
20
21
22
23
24
DRVDD
D2/3–
D2/3+
D4/5–
D4/5+
D6/7–
D6/7+
DRVDD
D8/9–
D8/9+
D10/11–
D10/11+
48
47
46
45
44
43
42
41
40
39
38
37
PDWN
RBIAS
VCM
AVDD
LVDS
VIN–
VIN+
LVDS_RS
DNC
DNC
VREF
SENSE
1
2
3
4
5
6
7
8
9
10
11
12
SYNC
CLK+
CLK–
AVDD
AVDD
OEB
DCO–
DCO+
DNC
DNC
D0/1–
D0/1+
DITHER
AVDD
SVDD
CSB
SCLK/DFS
SDIO/DCS
DRVDD
OR+
OR–
D12/13+
D12/13–
35
AVDD
36
34
33
32
31
30
29
28
27
26
25
AD9255
INTERLEAVED
LVDS
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
NOTES
1. DNC = DO NOT CONNECT.
2.
THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD
MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
08505-004
Figure 5. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)
Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No. Mnemonic Type Description
ADC Power Supplies
13, 20, 29 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal).
4, 5, 34, 36, 45 AVDD Supply Analog Power Supply (1.8 V Nominal).
33
SVDD
Supply
SPI Input/Output Voltage.
9, 10, 39, 40 DNC Do Not Connect.
0 AGND Ground
Analog Ground. The exposed thermal pad on the bottom of the package provides the
analog ground for the input. This exposed pad must be connected to ground for proper
operation.
ADC Analog
42 VIN+ Input Differential Analog Input Pin (+).
43 VIN− Input Differential Analog Input Pin (−).
38
VREF
Input/output
Voltage Reference Input/Output.
37 SENSE Input Voltage Reference Mode Select. See Table 11 for details.
47 RBIAS Input/output External Reference Bias Resistor.
46 VCM Output Common-Mode Level Bias Output for Analog Inputs.
2 CLK+ Input ADC Clock Input—True.
3 CLK− Input ADC Clock Input—Complement.
Digital Input
1 SYNC Input Digital Synchronization Pin. Slave mode only.
Digital Outputs
12 D0/1+ Output LVDS Output Data Bit 0/Bit 1 (LSB)—True.
11 D0/1− Output LVDS Output Data Bit 0/Bit 1 (LSB)—Complement.
15
D2/3+
Output
LVDS Output Data Bit 2/Bit 3—True.
14 D2/3− Output LVDS Output Data Bit 2/Bit 3—Complement.
17 D4/5+ Output LVDS Output Data Bit 4/Bit 5—True.
16 D4/5− Output LVDS Output Data Bit 4/Bit 5—Complement.
19 D6/7+ Output LVDS Output Data Bit 6/Bit 7—True.
18 D6/7− Output LVDS Output Data Bit 6/Bit 7—Complement.
22
D8/9+
Output
LVDS Output Data Bit 8/Bit 9 —True.
21 D8/9− Output LVDS Output Data Bit 8/Bit 9—Complement.