Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal LFCSP 48 VQ

14-Bit, 125 MSPS/105 MSPS/80 MSPS,

1.8 V Analog-to-Digital Converter

Data Sheet

AD9255

Rev. C Document Feedback

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FEATURES

SNR = 78.3 dBFS at 70 MHz and 125 MSPS

SFDR = 93 dBc at 70 MHz and 125 MSPS

Low power: 371 mW at 125 MSPS

1.8 V analog supply operation

1.8 V CMOS or LVDS output supply

Integer 1-to-8 input clock divider

IF sampling frequencies to 300 MHz

−153.4 dBm/Hz small signal input noise with 200 Ω input

impedance at 70 MHz and 125 MSPS

Optional on-chip dither

Programmable internal ADC voltage reference

Integrated ADC sample-and-hold inputs

Flexible analog input range: 1 V p-p to 2 V p-p

Differential analog inputs with 650 MHz bandwidth

ADC clock duty cycle stabilizer

Serial port control

User-configurable, built-in self-test (BIST) capability

Energy-saving power-down modes

APPLICATIONS

Communications

Multimode digital receivers (3G)

GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and

TD-SCDMA

Smart antenna systems

General-purpose software radios

Broadband data applications

Ultrasound equipment

PRODUCT HIGHLIGHTS

1. On-chip dither option for improved SFDR performance

with low power analog input.

2. Proprietary differential input that maintains excellent SNR

performance for input frequencies up to 300 MHz.

3. Operation from a single 1.8 V supply and a separate digital

output driver supply accommodating 1.8 V CMOS or

LVDS outputs.

4. Standard serial port interface (SPI) that supports various

product features and functions, such as data formatting

(offset binary, twos complement, or gray coding), enabling

the clock DCS, power-down, test modes, and voltage

reference mode.

5. Pin compatibility with the AD9265, allowing a simple

migration up to 16 bits.

FUNCTIONAL BLOCK DIAGRAM

14 14

DRVDD (1.8V)

D13 TO D0

OEB

DCO

DITHER

CLK+

CLK–

SYNC

CLOCK

MANAGEMENT

ADC

14-BIT

CORE

OUTPUT

STAGING

CMOS OR

LVDS

(DDR)

VCM

VREF

VIN+

VIN–

TRACK-AND-HOLD

REFERENCE

RBIASSENSE PDWN

SERIAL PORT

SVDD SCLK/

DFS

SDIO/

DCS

CSB

AGND AVDD (1.8V) LVDS LVDS_RS

AD9255

08505-001

Figure 1.

Summary of content (44 pages)

PAGE 1
4-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter AD9255 Data Sheet FEATURES APPLICATIONS SNR = 78.3 dBFS at 70 MHz and 125 MSPS SFDR = 93 dBc at 70 MHz and 125 MSPS Low power: 371 mW at 125 MSPS 1.8 V analog supply operation 1.8 V CMOS or LVDS output supply Integer 1-to-8 input clock divider IF sampling frequencies to 300 MHz −153.
PAGE 2
AD9255 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ....................................................................... 28 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 29 Product Highlights ................................................................
PAGE 3
Data Sheet AD9255 GENERAL DESCRIPTION The AD9255 is a 14-bit, 125 MSPS analog-to-digital converter (ADC). The AD9255 is designed to support communications applications where high performance combined with low cost, small size, and versatility is desired. The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic to provide 14-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range.
PAGE 4
AD9255 Data Sheet SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL)2 Integral Nonlinearity (INL)2 TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation at 1.
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Data Sheet AD9255 ADC AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 2. 1 Parameter SIGNAL-TO-NOISE-RATIO (SNR) fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz SIGNAL-TO-NOISE-AND DISTORTION (SINAD) fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.
PAGE 6
AD9255 1 Parameter WORST OTHER (HARMONIC OR SPUR) Without Dither fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz With On-Chip Dither fIN = 2.
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Data Sheet Parameter LOGIC INPUT (CSB) 1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT (SCLK/DFS) 2 High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = 1.
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AD9255 Data Sheet SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 4.
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Data Sheet AD9255 TIMING SPECIFICATIONS Table 5. Parameter SYNC TIMING REQUIREMENTS tSSYNC tHSYNC SPI TIMING REQUIREMENTS 1 tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO 1 Conditions Min Typ SYNC to rising edge of CLK setup time SYNC to rising edge of CLK hold time Max 0.30 0.
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AD9255 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to AGND SVDD to AGND VIN+, VIN− to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/DCS to AGND OEB to AGND PDWN to AGND LVDS to AGND LVDS_RS to AGND DITHER to AGND D0 through D13 to AGND DCO to AGND Environmental Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) Rating −0.
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Data Sheet AD9255 48 47 46 45 44 43 42 41 40 39 38 37 PDWN RBIAS VCM AVDD LVDS VIN– VIN+ LVDS_RS DNC DNC VREF SENSE PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SYNC CLK+ 1 2 PIN 1 INDICATOR CLK– 3 AVDD 4 AVDD 5 OEB 6 DNC 7 DCO 8 DNC 9 DNC 10 D0 (LSB) 11 D1 12 AD9255 AVDD DITHER AVDD SVDD CSB SCLK/DFS SDIO/DCS DRVDD DNC OR D13 (MSB) D12 NOTES 1. DNC = DO NOT CONNECT. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE INPUT.
PAGE 12
AD9255 Data Sheet Pin No. 22 23 24 25 26 27 8 SPI Control 31 30 32 ADC Configuration 6 35 Mnemonic D9 D10 D11 D12 D13 (MSB) OR DCO Type Output Output Output Output Output Output Output Description CMOS Output Data. CMOS Output Data. CMOS Output Data. CMOS Output Data. CMOS Output Data. Overrange Output. Data Clock Output. SCLK/DFS SDIO/DCS CSB Input Input/output Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
PAGE 13
AD9255 48 47 46 45 44 43 42 41 40 39 38 37 PDWN RBIAS VCM AVDD LVDS VIN– VIN+ LVDS_RS DNC DNC VREF SENSE Data Sheet SYNC CLK+ 1 2 AD9255 INTERLEAVED LVDS TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 AVDD DITHER AVDD SVDD CSB SCLK/DFS SDIO/DCS DRVDD OR+ OR– D12/13+ D12/13– NOTES 1. DNC = DO NOT CONNECT. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
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AD9255 Data Sheet Pin No. Mnemonic 24 D10/11+ 23 D10/11− 26 D12/13+ (MSB) 25 D12/13− (MSB) 28 OR+ 27 OR− 8 DCO+ 7 DCO− SPI Control 31 SCLK/DFS 30 SDIO/DCS 32 CSB ADC Configuration 6 OEB 35 DITHER Type Output Output Output Output Output Output Output Output Description LVDS Output Data Bit 10/Bit 11—True. LVDS Output Data Bit 10/Bit 11—Complement. LVDS Output Data Bit 12/Bit 13—True. LVDS Output Data Bit 12/Bit 13—Complement. LVDS Overrange Output—True. LVDS Overrange Output—Complement.
PAGE 15
Data Sheet AD9255 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, sample rate = 125 MSPS, DCS enabled, 1.0 V internal reference, 2 V p-p differential input, VIN = −1.0 dBFS, and 32k sample, TA = 25°C, unless otherwise noted.
PAGE 16
AD9255 Data Sheet 120 1.6M 0.62 LSB RMS SFDRFS (DITHER ON) 1.4M 110 NUMBER OF HITS SNR/SFDR (dBFS) 1.2M 100 SFDRFS (DITHER OFF) 90 1.0M 800k 600k SNRFS (DITHER OFF) 400k SNRFS (DITHER ON) 200k –90 –80 –70 –60 –40 –50 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) 0 08505-112 70 –100 N–3 N–1 N N+1 N+2 N+3 OUTPUT CODE Figure 12. AD9255-80 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 30 MHz with and without Dither Enabled Figure 15.
PAGE 17
Data Sheet AD9255 AMPLITUDE (dBFS) –40 –60 SECOND HARMONIC –80 THIRD HARMONIC –80 –120 20 30 40 50 –140 08505-118 10 0 10 0 105MSPS 70.1MHz @ –6dBFS –20 SNR = 72.9dB (78.9dBFS) SFDR = 91dBc –40 –40 AMPLITUDE (dBFS) 105MSPS 70.1MHz @ –1dBFS –20 SNR = 77.4dB (78.4dBFS) SFDR = 88.7dBc –60 SECOND HARMONIC –80 THIRD HARMONIC –60 –80 –100 –120 –120 30 40 50 FREQUENCY (MHz) –140 08505-119 –140 Figure 19. AD9255-105 Single-Tone FFT with fIN = 70.
PAGE 18
AD9255 Data Sheet 120 1.4M 0.63 LSB RMS SFDRFS (DITHER ON) 1.2M 110 NUMBER OF HITS SNR/SFDR (dBFS) 1.0M 100 SFDRFS (DITHER OFF) 90 800k 600k 400k SNRFS (DITHER OFF) 80 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) 0 08505-124 70 –100 N–3 N N+1 N+2 N+3 Figure 27. AD9255-105 Grounded Input Histogram 100 1.0 SFDR @ –40°C SFDR @ +25°C INL WITHOUT DITHER INL WITH DITHER 0.8 95 0.
PAGE 19
Data Sheet AD9255 AMPLITUDE (dBFS) –40 –60 SECOND HARMONIC THIRD HARMONIC SECOND HARMONIC –120 –120 20 30 40 50 60 FREQUENCY (MHz) –140 08505-130 10 0 AMPLITUDE (dBFS) SECOND HARMONIC –40 –60 THIRD HARMONIC –80 –100 –100 –120 –120 0 10 20 30 40 50 60 FREQUENCY (MHz) SECOND HARMONIC –140 08505-131 –140 0 10 20 30 –40 –40 AMPLITUDE (dBFS) 125MSPS 220.1MHz @ –1dBFS –20 SNR = 74.2dB (75.2dBFS) SFDR = 79.
PAGE 20
AD9255 Data Sheet 0 120 SFDR (dBFS) 100 SNR/SFDR (dBc AND dBFS) –40 –60 –80 SECOND HARMONIC THIRD HARMONIC –100 0 10 20 30 40 50 60 FREQUENCY (MHz) Figure 36. AD9255-125 Single-Tone FFT with fIN = 70.1 MHz at −6 dBFS with Dither Enabled 40 SNR (dBc) –60 –50 –40 –30 –20 –10 0 Figure 39. AD9255-125 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 2.
PAGE 21
Data Sheet AD9255 100 0 SFDR @ –40°C –20 SFDR/IMD3 (dBc AND dBFS) SFDR @ +25°C 90 SFDR @ +85°C 85 SNR @ –40°C 80 75 SNR @ +25°C SFDR (dBc) –40 IMD3 (dBc) –60 –80 –100 SFDR (dBFS) SNR @ +85°C 70 50 100 150 200 250 300 INPUT FREQUENCY (MHz) –140 –90 Figure 42. AD9255-125 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Temperature with 2 V p-p Full Scale –66 –54 –42 –30 –18 –6 INPUT AMPLITUDE (dBFS) Figure 45. AD9255-125 Two-Tone SFDR/IMD3 vs.
PAGE 22
AD9255 Data Sheet 105 0.50 100 DNL ERROR (LSB) SNR/SFDR (dBFS/dBc) 0.25 95 90 SFDR 85 0 –0.25 80 45 55 65 75 85 95 105 115 –0.50 08505-148 35 125 SAMPLE RATE (MSPS) 0 10,000 12,000 14,000 16,000 0.63 LSB RMS SFDR (dBc) SNR/SFDR (dBFS AND dBc) 90 1.0M 800k 600k 400k 80 SFDR (dBFS) 70 60 50 200k N–3 N–2 N–1 N N+1 N+2 N+3 OUTPUT CODE 40 0.75 08505-149 0 INL WITHOUT DITHER INL WITH DITHER 0.6 0.4 0.2 0 –0.2 –0.4 –0.
PAGE 23
Data Sheet AD9255 EQUIVALENT CIRCUITS DRVDD VIN+ OR VIN– 08505-005 08505-007 PAD Figure 57. Digital Output Figure 53. Equivalent Analog Input Circuit AVDD SVDD 0.9V 26kΩ 10kΩ CLK– 350Ω SDIO/DCS 08505-006 CLK+ 08505-008 10kΩ Figure 58. Equivalent SDIO/DCS Circuit Figure 54. Equivalent Clock Input Circuit AVDD SVDD 350Ω SCLK/DFS VREF 6kΩ 08505-009 08505-012 26kΩ Figure 55. Equivalent VREF Circuit Figure 59.
PAGE 24
AD9255 Data Sheet AVDD 350Ω PDWN DITHER, LVDS OR LVDS_RS 26kΩ 08505-063 08505-061 26kΩ Figure 61. Equivalent PDWN Circuit Figure 63. Equivalent DITHER, LVDS, and LVDS_RS Input Circuit DRVDD 26kΩ 350Ω 08505-062 OEB 350Ω Figure 62. Equivalent OEB Input Circuit Rev.
PAGE 25
Data Sheet AD9255 THEORY OF OPERATION Synchronization capability is provided to allow synchronized timing between multiple devices. Programming and control of the AD9255 are accomplished using a 3-wire SPI-compatible serial interface. ADC ARCHITECTURE The AD9255 architecture consists of a front-end sample-andhold input network, followed by a pipelined, switched-capacitor ADC. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic.
PAGE 26
AD9255 Data Sheet Dither Static Linearity The AD9255 has an optional dither mode that can be selected either using the DITHER pin or using the SPI bus. Dithering is the act of injecting a known but random amount of white noise, commonly referred to as dither, into the input of the ADC. Dithering has the effect of improving the local linearity at various points along the ADC transfer function.
PAGE 27
Data Sheet AD9255 Table 10. Example RC Network which SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 68). In this configuration, the input is ac-coupled and the CML is provided to each input through a 33 Ω resistor. These resistors compensate for losses in the input baluns to provide a 50 Ω impedance to the driver. Frequency Range (MHz) 0 to 100 100 to 300 R1 Series (Ω Each) 15 10 C1 Differential (pF) 18 10 C2 0.
PAGE 28
AD9255 Data Sheet VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD9255. The input range can be adjusted by varying the reference voltage applied to the AD9255, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are summarized in the sections that follow. The Reference Decoupling section describes the best practices PCB layout of the reference.
PAGE 29
Data Sheet AD9255 External Reference Operation Clock Input Options The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 73 shows the typical drift characteristics of the internal reference in 1.0 V mode. The AD9255 has a very flexible clock input structure. Clock input can be a CMOS, LVDS, LVPECL, or sine wave signal.
PAGE 30
AD9255 Data Sheet 0.1µF 0.1µF CLOCK INPUT CLK+ AD95xx 0.1µF 0.1µF ADC AD9255 CLK– 50kΩ 08505-051 CLOCK INPUT 100Ω LVDS DRIVER 50kΩ Figure 78. Differential LVDS Sample Clock (Up to the Rated Sample Rate) A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 78. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/ AD9518/AD9520/AD9522 clock drivers offer excellent jitter performance.
PAGE 31
Data Sheet AD9255 80 0.20 0.5 0.05ps IAVDD 75 0.16 0.4 SNR (dBc) 70 0.20ps 65 60 0.50ps 55 1.00ps 0.3 0.12 TOTAL POWER 0.2 0.08 0.1 0.04 SUPPLY CURRENT (A) TOTAL POWER (W) MEASURED IDRVDD 50 0 125 100 75 CLOCK FREQUENCY (MSPS) Figure 80. SNR vs. Input Frequency and Jitter 0.4 0.16 0.3 0.12 TOTAL POWER 0.2 0.08 0.1 0.
PAGE 32
AD9255 Data Sheet Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to normal operation. When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required.
PAGE 33
Data Sheet AD9255 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9255 includes built-in self-test features designed to enable verification of the integrity of the part as well as facilitate board level debugging. A built-in self-test (BIST) feature is included that verifies the integrity of the digital datapath of the AD9255. Various output test options are also provided to place predictable values on the outputs of the AD9255.
PAGE 34
AD9255 Data Sheet SERIAL PORT INTERFACE (SPI) The AD9255 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to, or read from, via the port.
PAGE 35
Data Sheet AD9255 CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES In applications that do not interface to the SPI control registers, the SDIO/DCS pin and the SCLK/DFS pin serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer and output data format feature control. In this mode, connect the CSB chip select to AVDD, which disables the serial port interface.
PAGE 36
AD9255 Data Sheet MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the transfer register (Address 0xFF); the ADC functions registers, including setup, control, and test (Address 0x08 to Address 0x30); and the digital feature control registers (Address 0x100).
PAGE 37
Data Sheet AD9255 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17. Memory Map Registers Addr.
PAGE 38
AD9255 Addr. (Hex) 0x14 Register Name Output mode 0x16 Data Sheet Bit 7 (MSB) Drive strength 0 = ANSI LVDS 1 = reduced LVDS Bit 6 Output type 0= CMOS 1 = LVDS Bit 5 Open Bit 4 Output enable bar Bit 3 Open Clock phase control Invert DCO clock Open Open Open Open 0x17 DCO output delay Open Open Open 0x18 VREF select Reference voltage selection 00 = 1.25 V p-p 01 = 1.5 V p-p 10 = 1.75 V p-p 11 = 2.
PAGE 39
Data Sheet AD9255 MEMORY MAP REGISTER DESCRIPTIONS and to ignore the rest. The clock divider sync enable bit (Address 0x100, Bit 1) resets after it syncs. For additional information about functions controlled in Register 0x00 to Register 0xFF, see AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Bit 1—Clock Divider Sync Enable Bits[7:3]—Reserved Bit 1 gates the sync pulse to the clock divider. The sync signal is enabled when Bit 1 is high and Bit 0 is high.
PAGE 40
AD9255 Data Sheet APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9255 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements that are needed for certain pins. Power and Ground Recommendations When connecting power to the AD9255, it is recommended that two separate 1.8 V supplies be used.
PAGE 41
Data Sheet AD9255 OUTLINE DIMENSIONS 0.30 0.23 0.18 0.60 MAX 0.60 MAX 37 PIN 1 INDICATOR 6.85 6.75 SQ 6.65 1 0.50 REF *5.55 5.50 SQ 5.45 EXPOSED PAD 12 25 0.50 0.40 0.30 TOP VIEW 1.00 0.85 0.80 13 24 BOTTOMVIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.22 MIN 5.50 REF 0.80 MAX 0.65 TYP 12° MAX PIN 1 INDICATOR 48 36 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
PAGE 42
AD9255 Data Sheet NOTES Rev.
PAGE 43
Data Sheet AD9255 NOTES Rev.