Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) Internal LFCSP 64 VQ

Octal, 14-Bit, 50 MSPS,

Serial LVDS, 1.8 V ADC

Data Sheet

AD9252

Rev. E

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Tel: 781.329.4700 www.analog.com

FEATURES

8 analog-to-digital converters (ADCs) integrated into 1 package

93.5 mW ADC power per channel at 50 MSPS

SNR = 73 dB (to Nyquist)

ENOB = 12 bits

SFDR = 84 dBc (to Nyquist)

Excellent linearity

DNL = ±0.4 LSB (typical); INL = ±1.5 LSB (typical)

Serial LVDS (ANSI-644, default)

Low power, reduced signal option (similar to IEEE 1596.3)

Data and frame clock outputs

325 MHz, full-power analog bandwidth

2 V p-p input voltage range

1.8 V supply operation

Serial port control

Full-chip and individual-channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Programmable clock and data alignment

Programmable output resolution

Standby mode

APPLICATIONS

Medical imaging and nondestructive ultrasound

Portable ultrasound and digital beam-forming systems

Quadrature radio receivers

Diversity radio receivers

Tape drives

Optical networking

Test equipment

GENERAL DESCRIPTION

The AD9252 is an octal, 14-bit, 50 MSPS ADC with an on-chip

sample-and-hold circuit designed for low cost, low power, small size,

and ease of use. Operating at a conversion rate of up to 50 MSPS,

it is optimized for outstanding dynamic performance and low

power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/

CMOS-/LVDS-compatible sample rate clock for full performance

operation. No external reference or driver components are

required for many applications.

The ADC automatically multiplies the sample rate clock for

the appropriate LVDS serial data rate. A data clock (DCO)

for capturing data on the output and a frame clock (FCO) for

signaling a new output byte are provided. Individual channel

power-down is supported and typically consumes less than

2 mW when all channels are disabled.

FUNCTIONAL BLOCK DIAGRAM

SERIAL

LVDS

REF

SELECT

AD9252

AGND

VIN – A

VIN + A

VIN – B

VIN + B

VIN – D

VIN + D

VIN – C

VIN + C

SENSE

VREF

DD DR

REFT

REFB

D – A

D + A

D – B

D + B

D – D

D + D

D – C

D + C

FCO–

FCO+

DCO+

DCO–

CLK+

CLK–

SERIAL PORT

INTERFACE

CSB

SCLK/

DTP

SDIO/

ODM

RBIAS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

ADC

DATA RATE

MULTIPLIER

0.5V

SERIAL

LVDS

VIN – E

VIN + E

VIN – F

VIN + F

VIN – H

VIN + H

VIN – G

VIN + G

D – E

D + E

D – F

D + F

D – H

D + H

D – G

D + G

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

ADC

06296-001

Figure 1.

The ADC contains several features designed to maximize

flexibility and minimize system cost, such as programmable

clock and data alignment and programmable digital test pattern

generation. The available digital test patterns include built-in

deterministic and pseudorandom patterns, along with custom user-

defined test patterns entered via the serial port interface (SPI).

The AD9252 is available in an RoHS compliant, 64-lead LFCSP. It is

specified over the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. Small Footprint. Eight ADCs are contained in a small package.

2. Low Power of 93.5 mW per Channel at 50 MSPS.

3. Ease of Use. A data clock output (DCO) operates up to

350 MHz and supports double data rate (DDR) operation.

4. User Flexibility. SPI control offers a wide range of flexible

features to meet specific system requirements.

5. Pin-Compatible Family. This includes the AD9212 (10-bit)

and AD9222 (12-bit).

Summary of content (52 pages)

PAGE 1
Octal, 14-Bit, 50 MSPS, Serial LVDS, 1.8 V ADC AD9252 Data Sheet 8 analog-to-digital converters (ADCs) integrated into 1 package 93.5 mW ADC power per channel at 50 MSPS SNR = 73 dB (to Nyquist) ENOB = 12 bits SFDR = 84 dBc (to Nyquist) Excellent linearity DNL = ±0.4 LSB (typical); INL = ±1.5 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3) Data and frame clock outputs 325 MHz, full-power analog bandwidth 2 V p-p input voltage range 1.
PAGE 2
AD9252 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Clock Input Considerations ...................................................... 19 Applications ....................................................................................... 1 Serial Port Interface (SPI) .............................................................. 27 General Description ..............................................................
PAGE 3
Data Sheet AD9252 SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Voltage (1 V Mode) REFERENCE Output Voltage Error (VREF = 1 V) Load Regulation @ 1.
PAGE 4
AD9252 Data Sheet AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz fIN = 19.
PAGE 5
Data Sheet AD9252 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3.
PAGE 6
AD9252 Data Sheet SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 4.
PAGE 7
Data Sheet AD9252 TIMING DIAGRAMS N–1 VIN ± x tA N tEH CLK– tEL CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA MSB N–9 D12 N–9 D11 N–9 D10 N–9 D9 N–9 D8 N–9 D7 N–9 D6 N–9 D5 N–9 D4 N–9 D3 N–9 D2 N–9 D1 N–9 D0 N–9 MSB N–8 D12 N–8 D+x Figure 2. 14-Bit Data Serial Stream (Default), MSB First N–1 VIN ± x tA N tEH CLK– tEL CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA MSB N–9 D10 N–9 D9 N–9 D8 N–9 D7 N–9 D6 N–9 D5 N–9 D+x Figure 3.
PAGE 8
AD9252 Data Sheet N–1 VIN ± x tA N tEL tEH CLK– CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA LSB N–9 D0 N–9 D1 N–9 D2 N–9 D3 N–9 D4 N–9 D5 N–9 D6 N–9 D+x Figure 4. 14-Bit Data Serial Stream, LSB First Rev.
PAGE 9
Data Sheet AD9252 ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE Table 5. Parameter ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs (D + x, D − x, DCO+, DCO−, FCO+, FCO−) CLK+, CLK− VIN + x, VIN − x SDIO/ODM PDWN, SCLK/DTP, CSB REFT, REFB, RBIAS VREF, SENSE ENVIRONMENTAL Operating Temperature Range (Ambient) Storage Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Table 6. With Respect To Rating AGND DRGND DRGND DRVDD DRGND −0.3 V to +2.0 V −0.3 V to +2.
PAGE 10
AD9252 Data Sheet 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VIN + F VIN – F AVDD VIN – E VIN + E AVDD REFT REFB VREF SENSE RBIAS VIN + D VIN – D AVDD VIN – C VIN + C PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) AD9252 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AVDD VIN + B VIN – B AVDD VIN – A VIN + A AVDD PDWN CSB SDIO/ODM SCLK/DTP AVDD DRGND DRVDD D+A D–A NOTES 1.
PAGE 11
Data Sheet Pin No.
PAGE 12
AD9252 Data Sheet EQUIVALENT CIRCUITS DRVDD V V D–x D+x 06296-006 V DRGND Figure 9. Equivalent Digital Output Circuit Figure 6. Equivalent Analog Input Circuit CLK+ V 06296-009 VIN ± x 10Ω 10kΩ 1.25V 10kΩ SCLK/DTP OR PDWN 10Ω 1kΩ 30kΩ 06296-010 06296-007 CLK– Figure 10. Equivalent SCLK/DTP or PDWN Input Circuit Figure 7. Equivalent Clock Input Circuit RBIAS 30kΩ 06296-011 350Ω 06296-008 SDIO/ODM 100Ω Figure 11. Equivalent RBIAS Circuit Figure 8.
PAGE 13
Data Sheet AD9252 AVDD 70kΩ CSB 1kΩ 6kΩ Figure 12. Equivalent CSB Input Circuit Figure 14. Equivalent VREF Circuit 1kΩ 06296-013 SENSE 06296-014 06296-012 VREF Figure 13. Equivalent SENSE Circuit Rev.
PAGE 14
AD9252 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0 AIN = –0.5dBFS SNR = 71.16dB ENOB = 11.53 BITS –20 SFDR = 72.92dBc AMPLITUDE (dBFS) –20 –40 –60 –80 –60 –80 0 5 10 15 20 25 FREQUENCY (MHz) –120 06296-048 –120 0 5 10 15 25 20 FREQUENCY (MHz) Figure 15. Single-Tone 32k FFT with fIN = 2.3 MHz, fSAMPLE = 50 MSPS 06296-051 –100 –100 Figure 18. Single-Tone 32k FFT with fIN = 120 MHz, fSAMPLE = 50 MSPS 90 0 AIN = –0.5dBFS SNR = 72.98dB ENOB = 11.83 BITS –20 SFDR = 83.
PAGE 15
Data Sheet AD9252 90 0 AIN1 AND AIN2 = –7dBFS SFDR = 83.64dB IMD2 = 95.57dBc –20 IMD3 = 84.26dBc 80 SFDR AMPLITUDE (dBFS) SNR/SFDR (dB) 70 60 50 80dB REFERENCE 40 –40 –60 –80 SNR 30 –100 –50 –40 –30 –20 ANALOG INPUT LEVEL (dBFS) –10 0 –120 0 Figure 21. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 50 MSPS 5 10 15 FREQUENCY (MHz) 20 25 06296-044 10 –60 06296-041 20 Figure 24.
PAGE 16
AD9252 Data Sheet 2.0 1.8 1.5 1.6 NUMBER OF HITS (Millions) 1.047LSB rms 1.0 0 –0.5 –1.0 –1.5 1.2 1.0 0.8 0.6 0.4 0.2 0 2000 4000 6000 8000 10000 12000 14000 16000 CODE 0 06296-053 –2.0 N–3 N–1 N N+1 N+2 N+3 CODE Figure 27. INL, fIN = 2.3 MHz, fSAMPLE = 50 MSPS Figure 30. Input-Referred Noise Histogram, fSAMPLE = 50 MSPS 1.0 0 NPR = 62.5dB NOTCH = 18.0MHz NOTCH WIDTH = 2.3MHz 0.8 –20 0.6 AMPLITUDE (dBFS) 0.4 DNL (LSB) N–2 06296-054 INL (LSB) 0.5 1.4 0.2 0 –0.2 –0.
PAGE 17
Data Sheet AD9252 THEORY OF OPERATION The AD9252 architecture consists of a pipelined ADC divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic.
PAGE 18
AD9252 Data Sheet ADT1-1WT 1:1 Z RATIO For best dynamic performance, the source impedances driving VIN + x and VIN − x should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates the positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core.
PAGE 19
Data Sheet AD9252 For optimum performance, the AD9252 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally and require no additional biasing. Figure 40 shows the preferred method for clocking the AD9252. The low jitter clock source is converted from single-ended to differential using an RF transformer.
PAGE 20
AD9252 Data Sheet Clock Jitter Considerations Power Dissipation and Power-Down Mode High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by As shown in Figure 46, the power dissipated by the AD9252 is proportional to its sample rate.
PAGE 21
Data Sheet AD9252 By asserting the PDWN pin high, the AD9252 is placed into power-down mode. In this state, the ADC typically dissipates 11 mW. During power-down, the LVDS output drivers are placed into a high impedance state. The AD9252 returns to normal operating mode when the PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. recommended that the trace length be no longer than 24 inches and that the differential output traces be kept close together and at equal lengths.
PAGE 22
AD9252 EYE: ALL BITS 400 ULS: 12071/12071 EYE DIAGRAM VOLTAGE (mV) EYE DIAGRAM VOLTAGE (mV) 400 300 200 100 0 –100 –200 –300 –400 –500 –1.0ns –0.5ns 0ns 0.5ns 1.0ns 0 –100 –200 –300 80 80 70 70 60 50 40 30 20 500 –50ps 0ps 50ps 100ps 150ps 06296-030 –100ps EYE: ALL BITS 0ns 0.5ns 1.0ns 1.5ns –100ps –50ps 0ps 50ps 100ps 150ps 50 40 30 20 Figure 50.
PAGE 23
Data Sheet AD9252 Two output clocks are provided to assist in capturing data from the AD9252. The DCO is used to clock the output data and is equal to seven times the sample clock (CLK) rate. Data is clocked out of the AD9252 and must be captured on the rising and falling edges of the DCO that supports double data rate (DDR) capturing. The FCO is used to signal the start of a new output byte and is equal to the sample clock rate. See the timing diagram shown in Figure 2 for more information. Table 9.
PAGE 24
AD9252 Data Sheet When the SPI is used, the DCO phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO+ and DCO− timing, as shown in Figure 2, is 90° relative to the output data edge. An 8-, 10-, and 12-bit serial stream can also be initiated from the SPI. This allows the user to implement different serial stream to test the device’s compatibility with lower and higher resolution systems.
PAGE 25
Data Sheet AD9252 CSB Pin VIN + x The CSB pin should be tied to AVDD for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. This pin is both 1.8 V and 3.3 V tolerant. VIN – x REFT 0.1µF ADC CORE 0.1µF 4.7µF REFB RBIAS Pin 0.1µF VREF 1µF 0.1µF 0.5V SELECT LOGIC SENSE 06296-031 To set the internal core bias current of the ADC, place a resistor that is nominally equal to 10.0 kΩ between the RBIAS pin and ground.
PAGE 26
AD9252 Data Sheet External Reference Operation 0.02 –0.02 –0.04 –0.06 –0.08 –0.10 –0.12 –0.14 –0.16 –0.18 –40 –20 0 20 40 TEMPERATURE (°C) Figure 54. Typical VREF Drift Rev. E | Page 26 of 52 60 80 06296-060 When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. The external reference is loaded with an equivalent 6 kΩ load.
PAGE 27
Data Sheet AD9252 SERIAL PORT INTERFACE (SPI) The AD9252 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This may provide the user with additional flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port.
PAGE 28
1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 0 10 20 30 40 50 60 70 80 90 100 NUMBER OF SDIO PINS CONNECTED TOGETHER 06296-059 Data Sheet VOH (V) AD9252 Figure 55. SDIO Pin Loading tDS tS tHI tCLK tDH tH tLO CSB SCLK DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE 06296-033 SDIO DON’T CARE DON’T CARE Figure 56. Serial Timing Details Table 15.
PAGE 29
Data Sheet AD9252 MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS Each row in the memory map register table (Table 16) has eight address locations. The memory map is divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device index and transfer register map (Address 0x04, Address 0x05, and Address 0xFF), and the ADC functions register map (Address 0x08 to Address 0x22).
PAGE 30
AD9252 Data Sheet Table 16. Memory Map Register 1 Addr.
PAGE 31
Data Sheet AD9252 Addr. (Hex) 14 Parameter Name output_mode (MSB) Bit 7 X 15 output_adjust 16 Bit 5 X X Bit 6 0 = LVDS ANSI-644 (default) 1 = LVDS low power, (IEEE 1596.
PAGE 32
AD9252 Data Sheet APPLICATIONS INFORMATION Exposed Paddle Thermal Heat Slug Recommendations DESIGN GUIDELINES Before starting design and layout of the AD9252 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and Ground Recommendations When connecting power to the AD9252, it is recommended that two separate 1.
PAGE 33
Data Sheet AD9252 EVALUATION BOARD board individually. Use P702 to connect a different supply for each section. At least one 1.8 V supply is needed for AVDD_DUT and DRVDD_DUT; however, it is recommended that separate supplies be used for both analog and digital signals and that each supply have a current capability of 1 A. To operate the evaluation board using the VGA option, a separate 5.0 V analog supply (AVDD_5 V) is needed.
PAGE 34
AD9252 Data Sheet A differential LVPECL clock can also be used to clock the ADC input using the AD9515 (U401). Populate R406 and R407 with 0 Ω resistors, and remove R215 and R216 to disconnect the default clock path inputs. In addition, populate C205 and C206 with a 0.1 μF capacitor, and remove C409 and C410 to disconnect the default clock path outputs. The AD9515 has many pin-strappable options that are set to a default mode of operation.
PAGE 35
Data Sheet AD9252 To configure the analog input to drive the VGA instead of the default transformer option, the following components need to be removed and/or changed. • • • Remove R102, R115, R128, R141, R161, R162, R163, R164, R202, R208, R218, R225, R234, R241, R252, R259, T101, T102, T103, T104, T201, T202, T203, and T204 in the default analog input path. Remove L507, L508, L511, L512, L515, L516, L519, L520, L607, L608, L611, L612, L615, L616, L619, and L620 on the AD8334 analog outputs.
PAGE 36
Rev. E | Page 36 of 52 Channel A P101 Figure 62. Evaluation Board Schematic, DUT Analog Inputs VGA Input Connection R115 64.9Ω R114 0Ω−DNP INH2 R102 64.9Ω R101 0Ω−DNP DNP: DO NOT POPULATE. Ain P103 Channel B Ain INH1 VGA Input Connection Ain DNP P104 Ain 0Ω R117 R103 0Ω C109 0.1µF C108 0.1µF AVDD_DUT R116 0Ω FB104 10Ω E102 R125 1KΩ R126 1kΩ 1 R113 3 2 C114 0.1µF 0Ω−DNP R124 4 5 6 R118 0Ω−DNP C107 0.
PAGE 37
Rev. E | Page 37 of 52 Figure 63. Evaluation Board Schematic, DUT Analog Inputs (Continued) R218 64.9Ω R217 0Ω−DNP DNP P204 Ain Ain VGA Input Connection INH6 R202 64.9Ω R201 0Ω−DNP DNP: DO NOT POPULATE. Ain P203 Channel F P201 Channel E Ain VGA Input Connection INH5 R203 0Ω E202 C209 0.1µF R232 1kΩ 1kΩ R231 1 CH_F CM6 C208 0.1µF CH_F AVDD_DUT R219 0Ω R220 0Ω FB204 10Ω 1 R205 0Ω−DNP 4 3 3 2 0.1µF C214 CM6 0Ω−DNP 4 R222 5 1 T202 6 R221 0Ω−DNP 0.
PAGE 38
Rev. E | Page 38 of 52 16 AVDD D+H D−H DRVDD DRGND D+C VIN+D D−C D+D RBIAS D−D FCO+ FCO− DCO+ AVDD DCO− D+E VIN+E D−E VIN−E D+F AVDD VIN−F D+G D−F VIN+F D−G 30 28 29 27 26 25 24 22 23 21 20 18 CHC CHB CHD CHC CHD FCO FCO Figure 64. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface R308 470kΩ VIN−D CHB C305 0.1µF VOUT AVDD 32 ADR510ARTZ 1.0V D−B 31 TRIM/NC D+B R310 10kΩ R309 4.
PAGE 39
Figure 65. Evaluation Board Schematic, Clock Circuitry Rev. E | Page 39 of 52 DNP: DO NOT POPULATE. 0Ω 1 6 C411 0.1µF R418 0Ω 7 S6 HSMS-2812-TR1G CR401 S7 10 R405 0Ω 9 S8 11 5 4 8 S9 S5 12 2 VREF 3 S10 S10 S9 S4 S1 S2 14 R416 1 SIGNAL=DNC;27,28 SIGNAL=AVDD_3.3V;4,17,20,21,24,26,29,30 S8 T401 E401 GND_PAD AD9515BCPZ S7 15 0Ω R415 R417 0Ω SYNCB CLKB CLK U401 S6 13 C403 0.1µF OPT_CLK R413 10kΩ 5 3 2 AVDD_3.3V S5 16 Enc R404 49.9Ω C402 0.
PAGE 40
1 CW C515 0.018µF L502 120nH GND VG12 Variable Gain Circuit (0−1.0V DC) External Variable Gain Drive Rev. E | Page 40 of 52 R508 274Ω INH1 C524 0.1µF 16 15 INH3 LMD3 VIN4 LOP4 VIP4 LON4 COM4X LMD1 LMD4 INH1 INH4 COM1 COM4 COM3 L501 120nH 0.1µF C513 27 26 24 23 19 18 R509 274Ω VG12 VG34 External Variable Gain Drive Figure 66. Evaluation Board Schematic, Optional DUT Analog Input Drive C532 0.1µF VPS4 25 VG34 AVDD_5V 22 17 C527 0.
PAGE 41
1 2 EXT VG JP601 CW GND VG56 EXT VG L602 120nH Variable Gain Circuit (0−1.0V DC) External Variable Gain Drive Rev. E | Page 41 of 52 R608 274Ω INH5 C624 0.1µF 16 15 INH3 LMD3 COM3X 30 61 LMD1 LMD4 INH1 INH4 62 COM1 L601 120nH 0.1µF C613 AVDD_5V 31 GAIN34 VPS4 VIN4 25 LOP4 VIP4 24 COM4 20 19 R609 274Ω 18 17 GND VG78 VG56 External Variable Gain Drive Figure 67. Evaluation Board Schematic, Optional DUT Analog Input Drive (Continued) C632 0.
PAGE 42
2 OPTIONAL GREEN GP0 7 8 MCLR/GP3 9 10 Rev. E | Page 42 of 52 Figure 68. Evaluation Board Schematic, Power Supply Inputs and SPI Interface Circuitry 1 GND 1 2 OUT OUT 4 C717 1µF L706 10µH C715 1µF L705 10µH DUT_DRVDD DUT_AVDD R715 10kΩ C721 1µF PWR_IN C719 1µF PWR_IN R714 10kΩ 3 IN IN U703 2 GND 3 A2 1 A1 Y1 6 ADP3339AKCZ−5-RL7 2 OUT 4 OUT 2 OUT 4 OUT Y2 4 VCC 5 ADP3339AKCZ−3.3-RL U705 U706 3 5 VCC Y2 4 Y1 6 NC7WZ16P6X_NL U702 GND DNP: DO NOT POPULATE.
PAGE 43
AD9252 06296-079 Data Sheet Figure 69. Evaluation Board Layout, Primary Side Rev.
PAGE 44
Data Sheet 06296-080 AD9252 Figure 70. Evaluation Board Layout, Ground Plane Rev.
PAGE 45
AD9252 06296-081 Data Sheet Figure 71. Evaluation Board Layout, Power Plane Rev.
PAGE 46
Data Sheet 06296-082 AD9252 Figure 72. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev.
PAGE 47
Data Sheet AD9252 Table 17.
PAGE 48
AD9252 Item 8 Qty per Board 8 9 1 10 9 11 16 12 4 13 Data Sheet Reference Designator C503, C514, C520, C526, C603, C614, C620, C626 C704 Device Capacitor Package 402 Value 22 pF, ceramic, NPO, 5% tol, 50 V Manufacturer Murata Manufacturer Part Number GRM1555C1H220JZ01D Capacitor 1206 ROHM Co., Ltd. TCA1C106M8R Capacitor 603 10 μF, tantalum, 16 V, 20% tol 1 μF, ceramic, X5R, 6.3 V, 10% tol Murata GRM188R61C105KA93D Capacitor 805 0.
PAGE 49
Data Sheet Item 26 Qty per Board 32 27 1 28 9 29 Reference Designator L505, L506, L507, L508, L509, L510, L511, L512, L513, L514, L515, L516, L517, L518, L519, L520, L605, L606, L607, L608, L609, L610, L611, L612, L613, L614, L615, L616, L617, L618, L619, L620 OSC401 AD9252 Manufacturer Part Number NRC04Z0TRF Device Resistor Package 805 Value 0 Ω, 1/8 W, 5% tol Manufacturer NIC Components Corp.
PAGE 50
AD9252 Data Sheet Item 37 Qty per Board 8 38 3 Reference Designator R161, R162, R163, R164, R208, R225, R241, R259 R303, R305, R306 39 1 40 41 Device Resistor Package 402 Value 499 Ω, 1/16 W, 1% tol Resistor 402 100 kΩ, 1/16 W, 1% tol R414 Resistor 402 4.12 kΩ, 1/16W, 1% tol 1 1 R404 R309 Resistor Resistor 402 402 49.9 Ω, 1/16 W, 0.5% tol 4.
PAGE 51
Data Sheet Item 55 Qty per Board 9 56 2 Reference Designator T101, T102, T103, T104, T201, T202, T203, T204, T401 U704, U707 57 2 58 59 60 AD9252 Device Transformer Package CD542 IC SOT-223 U501, U601 IC CP-64-3 1 1 1 U706 U705 U301 IC IC IC SOT-223 SOT-223 CP-64-3 61 1 U302 IC SOT-23 62 1 U401 IC 63 1 U702 IC 64 1 U703 IC 65 1 U701 IC LFCSP CP-32-2 SC70, MAA06A SC70, MAA06A 8-SOIC 1 Value ADT1-1WT+, 1:1 impedance ratio transformer ADP3339AKC-1.8-RL, 1.5 A, 1.
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AD9252 Data Sheet OUTLINE DIMENSIONS 0.60 MAX 9.00 BSC SQ 0.60 MAX 48 64 1 49 PIN 1 INDICATOR PIN 1 INDICATOR 0.50 BSC 0.50 0.40 0.30 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.22 MIN 7.50 REF 0.80 MAX 0.65 TYP 12° MAX 16 17 33 32 TOP VIEW 1.00 0.85 0.80 7.55 7.50 SQ 7.45 EXPOSED PAD (BOTTOM VIEW) 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.