Datasheet

AD9251
Rev. A | Page 8 of 36
TIMING SPECIFICATIONS
Table 5.
Parameter Conditions Min Typ Max Unit
SYNC TIMING REQUIREMENTS
t
SSYNC
SYNC to rising edge of CLK setup time 0.24 ns
t
HSYNC
SYNC to rising edge of CLK hold time 0.40 ns
SPI TIMING REQUIREMENTS
t
DS
Setup time between the data and the rising edge of SCLK 2 ns
t
DH
Hold time between the data and the rising edge of SCLK 2 ns
t
CLK
Period of the SCLK 40 ns
t
S
Setup time between CSB and SCLK 2 ns
t
H
Hold time between CSB and SCLK 2 ns
t
HIGH
SCLK pulse width high 10 ns
t
LOW
SCLK pulse width low 10 ns
t
EN_SDIO
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
10 ns
t
DIS_SDIO
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge
10 ns
Timing Diagrams
t
PD
t
SKEW
t
CH
t
DCO
t
CLK
N – 9
N – 1
N + 1
N + 2
N + 3
N + 5
N + 4
N
N – 8N – 7N – 6N – 5
VIN
CLK+
CLK–
CH A/CH B DATA
DCOA/DCOB
t
A
07938-002
Figure 2. CMOS Output Data Timing
t
PD
t
SKEW
t
CH
t
DCO
t
CLK
CH A
N – 9
CH B
N – 9
CH A
N – 8
CH B
N – 8
CH A
N – 7
CH B
N – 7
CH A
N – 6
CH B
N – 6
CH A
N – 5
N – 1
N + 1
N + 2
N + 3
N + 5
N + 4
N
VIN
CLK+
CLK–
CH A/CH B DATA
DCOA/DCOB
t
A
07938-003
Figure 3. CMOS Interleaved Output Timing