Datasheet

AD9248
Rev. B | Page 7 of 48
SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; A
IN
= −0.5 dBFS differential input, 1.0 V internal reference,
T
MIN
to T
MAX
, DCS enabled, unless otherwise noted.
Table 4.
Test AD9248BST/BCP-20 AD9248BST/BCP-40 AD9248BST/BCP-65
Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 20 40 65 MSPS
Minimum Conversion Rate Full V 1 1 1 MSPS
CLK Period Full V 50.0 25.0 15.4 ns
CLK Pulse-Width High
1
Full V 15.0 8.8 6.2 ns
CLK Pulse-Width Low
1
Full V 15.0 8.8 6.2 ns
DATA OUTPUT PARAMETER
Output Delay
2
(t
PD
) Full VI 2 3.5 6 2 3.5 6 2 3.5 6 ns
Pipeline Delay (Latency) Full V 7 7 7 Cycles
Aperture Delay (t
A
) Full V 1.0 1.0 1.0 ns
Aperture Uncertainty (t
J
) Full V 0.5 0.5 0.5 ps rms
Wake-Up Time
3
Full V 2.5 2.5 2.5 ms
OUT-OF-RANGE RECOVERY TIME Full V 2 2 2 Cycles
1
The AD9248-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 24).
2
Output delay is measured from clock 50% transition to data 50% transition, with a 5 pF load on each output.
3
Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
A
NALOG
INPUT
CLOCK
DATA
OUT
N–9 N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
MIN 2.0ns,
MAX 6.0ns
t
PD
=
04446-002
Figure 2. Timing Diagram