Datasheet

AD9245 Data Sheet
Rev. E | Page 8 of 32
SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted.
Table 6.
Parameter
AD9245BCP-20 AD9245BCP-40 AD9245BCP-65 AD9245BCP-80 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
CLOCK INPUT PARAMETERS
Maximum Conversion Rate 20 40 65 80 MSPS
Minimum Conversion Rate 1 1 1 1 MSPS
CLK Period 50.0 25.0 15.4 12.5 ns
CLK Pulse Width High
1
15.0 8.8 6.2 4.6 ns
CLK Pulse Width Low
1
15.0 8.8 6.2 4.6 ns
DATA OUTPUT PARAMETERS
Output Delay
2
(t
PD
) 3.5 3.5 3.5 4.2 ns
Pipeline Delay (Latency) 7 7 7 7 Cycles
Aperture Delay (t
A
) 1.0 1.0 1.0 1.0 ns
Aperture Uncertainty Jitter (t
J
) 0.5 0.5 0.5 0.3 ps rms
Wake-Up Time
3
3.0 3.0 3.0 7.0 ms
OUT-OF-RANGE RECOVERY TIME 1 1 2 2 Cycles
1
For the AD9245BCP-65 and AD9245BCP-80 models only, with duty cycle stabilizer enabled. DCS function not applicable for AD9245BCP-20 and AD9245BCP-40
models.
2
Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
3
Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
t
A
2.0ns MIN
t
PD
= 6.0ns MAX
03583-002
N–9N–8N–7N–6N–5N–4N–3N–2N–1 N
ANALOG
INPUT
CLK
DATA
OUT
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
Figure 2. Timing Diagram