Datasheet

Data Sheet AD9245
Rev. E | Page 25 of 32
03583-052
C10
10µF
C4
10µF
C3
10µF
C25
10
µF
C32
0.001µF
C33
0.1µF
C14
0.001
µF
VDL
DRVDD AVDD
GND
GND
AV
DD
DUT BYPASSING
CLOCK TIMING
ADJUSTMENTS
FOR A BUFFERED ENCODE USE R28
FOR A DIRECT ENCODE USE R27
ANALOG BYPASSING DIGIT
AL BYPASSING LATCH BYPASSING
GND
DRVDD
C41 0.1µF
C2
10µ
F
C30
0.001
µF
C31 0.1µF
C46
10
µF
C34
0.1µ
F
C36 0.1µF
C38
0.001µF
C1
0.1
µF
C47 0.1µF
C48 0.001
µF
C49 0.001µF
C20
10µF
C37
0.1µ
F
C40
0.001µF
GND
GND
VAMP
VDL
C39 0.001µF
ENCX
CLK
ENC
ENCODE
R27 0
Ω
R32
1k
Ω
R23
0
Ω
R37
0
Ω
R22
0
Ω
R28 0
Ω
E50
E51
ENC
VDL
VDL
VDL
E52
E53
E31 E35 E43
E44
GND
GND
GND
PWR
GND
CLKLAT/DAC
VDL
GND
VDL
GND
C43 0.1
µF
R31 1kΩ
R20
1k
Ω
R21 1k
Ω
R24 1k
Ω
R30 1kΩ
R29 50Ω
GND
J2
GND VDL
GND
1
1Y
U5
4Y
2Y
3Y
2 4 5
9
10
3
6
7 8
11
14
12
13
74VCX86
ENCX
1B
1A
2B
2A
3B
3A
4B
4A
DR
SCHEMATIC SHOWS TWO GATE DELAY SETUP.
FOR ONE DELAY, REMOVE R22 AND R37 AND ATTACH Rx (Rx = 0Ω
).
Rx DNP
LA
TCH BYPASSING
Figure 51. LFCSP Evaluation Board Schematic—Clock Input