Datasheet

AD9244
Rev. C | Page 6 of 36
Test AD9244BST-65 AD9244BST-40
Parameter Temp Level Min Typ Max Min Typ Max Unit
DIGITAL OUTPUTS (DRVDD = 3 V)
2
Logic 1 Voltage (I
OH
= 50 µA) Full IV 2.95 2.95 V
Logic 0 Voltage (I
OL
= 50 µA) Full IV 0.05 0.05 V
Logic 1 Voltage (I
OH
= 0.5 mA) Full IV 2.8 2.8 V
Logic 0 Voltage (I
OL
= 1.6 mA) Full IV 0.4 0.4 V
1
See the Clock Overview section for more details.
2
Output voltage levels measured with 5 pF load on each output.
SWITCHING SPECIFICATIONS
AVDD = 5 V, DRVDD = 3 V, unless otherwise noted.
Table 4.
Test AD9244BST-65 AD9244BST-40
Parameter Temp Level Min Typ Max Min Typ Max Unit
CLOCK INPUT PARAMETERS
Maximum Conversion Rate Full VI 65 40 MHz
Minimum Conversion Rate Full V 500 500 kHz
Clock Period
1
Full V 15.4 25 ns
Clock Pulse Width High
2
Full V 4 4 ns
Clock Pulse Width Low
2
Full V 4 4 ns
Clock Pulse Width High
3
Full V 6.9 11.3 ns
Clock Pulse Width Low
3
Full V 6.9 11.3 ns
DATA OUTPUT PARAMETERS
Output Delay (t
PD
)
4
Full V 3.5 7 3.5 7 ns
Pipeline Delay (Latency) Full V 8 8 Clock cycles
Aperture Delay (t
A
) Full V 1.5 1.5 ns
Aperture Uncertainty (Jitter) Full V 0.3 0.3 ps rms
Output Enable Delay Full V 15 15 ns
OUT-OF-RANGE RECOVERY TIME Full V 2 1 Clock cycles
1
The clock period can be extended to 2 µs with no degradation in specified performance at 25°C.
2
With duty cycle stabilizer enabled.
3
With duty cycle stabilizer disabled.
4
Measured from clock 50% transition to data 50% transition with 5 pF load on each output.
N
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
N + 8
N + 9
ANALOG INPUT
CLOCK
DATA OUT
t
PD
t
A
N – 9 N – 8 N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1
02404-002
Figure 2. Input Timing