Datasheet

Data Sheet AD9237
Rev. B | Page 3 of 24
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, −0.5 dBFS input, 1.0 V internal reference, T
MIN
to T
MAX
,
unless otherwise noted.
Table 1.
AD9237BCP-20 AD9237BCP-40 AD9237BCP-65
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION
12
12
12
Bits
ACCURACY
No Missing Codes Guaranteed 12 12 12 Bits
Offset Error
±1.30
±1.95
±1.30
±1.95
±1.30
±1.95
% FSR
Gain Error
1
±0.70 ±2.10 ±0.75 ±2.10 ±1.05 ±2.25 % FSR
Differential Nonlinearity (DNL)
2
±0.70 ±0.95 ±0.70 ±0.95 −1.00 ±0.70 +1.25 LSB
Integral Nonlinearity (INL)
2
±0.90 ±1.35 ±0.90 ±1.35 ±0.90 ±2.00 LSB
TEMPERATURE DRIFT
Offset Error ±2 ±2 ±2 ppm/°C
Gain Error
1
±12 ±12 ±12 ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode) ±5 ±25 ±5 ±25 ±5 ±25 mV
Load Regulation @ 1.0 mA 0.8 0.8 0.8 mV
Output Voltage Error (0.5 V Mode) ±2.5 ±2.5 ±2.5 mV
Load Regulation @ 0.5 mA
0.1
0.1
0.1
mV
Reference Input Resistance 7 7 7 kΩ
INPUT REFERRED NOISE
VREF = 0.5 V 1.35 1.35 1.35 LSB rms
VREF = 1.0 V 0.70 0.70 0.70 LSB rms
ANALOG INPUT
Input Span
VREF = 0.5 V; MODE2 = 0 V 1 1 1 V p-p
VREF = 1.0 V; MODE2 = 0 V 2 2 2 V p-p
VREF = 0.5 V; MODE2 = AVDD 2 2 2 V p-p
VREF = 1.0 V; MODE2 = AVDD 4 4 4 V p-p
Input Capacitance
3
7
7
7
pF
POWER SUPPLIES
Supply Voltages
AVDD 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V
DRVDD 2.25 2.5 3.6 2.25 2.5 3.6 2.25 2.5 3.6 V
Supply Current
IAVDD
2
30.5 45.5 64.5 mA
IDRVDD
2
3.0 4.5 5.5 mA
PSRR ±0.01 ±0.01 ±0.01 % FSR
POWER CONSUMPTION
DC Input
4
85 135 190 mW
Sine Wave Input
2
100
120
150
180
210
270
mW
Power-Down Mode 1 1 1 mW
Standby Power 20 20 20 mW
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
2
Measured at maximum clock rate, f
IN
= 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.
4
Measured with dc input at maximum clock rate.