Datasheet

AD9236 Data Sheet
Rev. C | Page 6 of 36
SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted.
Table 4.
Parameter Temp Test Level
AD9236BRU/AD9236BCP
Unit Min Typ Max
CLOCK INPUT PARAMETERS
Maximum Conversion Rate Full VI 80 MSPS
Minimum Conversion Rate Full V 1 MSPS
CLK Period Full V 12.5 ns
CLK Pulse Width High
1
Full V 4.0 ns
CLK Pulse Width Low
1
Full V 4.0 ns
DATA OUTPUT PARAMETERS
Output Propagation Delay (t
PD
)
2
Full V 3.5 ns
Pipeline Delay (Latency) Full V 7 Cycles
Aperture Delay (t
A
) Full V 1.0 ns
Aperture Uncertainty (Jitter, t
J
) Full V 0.3 ps rms
Wake-Up Time
3
Full V 7 ms
OUT OF RANGE RECOVERY TIME Full V 2 Cycles
1
With duty cycle stabilizer (DCS) enabled.
2
Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
3
Wake-up time is dependant on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
t
A
2.0ns MIN
t
PD
= 6.0ns MAX
03066-0-002
N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N
ANALOG
INPUT
CLK
DATA
OUT
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
Figure 2. Timing Diagram
Table 5. Explanation of Test Levels
Test Level Definitions
I 100% production tested.
II 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.