Datasheet

Data Sheet AD9236
Rev. C | Page 29 of 36
03066-A-052
C10
10F
C4
10F
C3
10F
C25
10F
C32
0.001F
C33
0.1F
C14
0.001F
VDL
DRVDD AVDD
GND
GND
AVDD
DUT BYPASSING
CLOCK TIMING ADJUSTMENTS
FOR A BUFFERED ENCODE USE R28
FOR A DIRECT ENCODE USE R27
ANALOG BYPASSING DIGITAL BYPASSING LATCH BYPASSING
GND
DRVDD
C41 0.1F
C2
10F
C30
0.001F
C31 0.1F
C46
10F
C34 0.1F
C36 0.1F
C38 0.001F
C1 0.1F
C47 0.1F
C48 0.001F
C49 0.001F
C20
10F
C37
0.1F
C40
0.001F
GND
GND
VAMP
VDL
C39 0.001F
ENCX
CLK
ENC
ENCODE
R27 0
R32 1k
R23
0
R37 25
Rx DNP
R22 0
R28 0
E50
E51
ENC
VDL
VDL
VDL
E52 E53
E31 E35 E43 E44
GND
GND
GND
PWR
GND
CLKLAT/DAC
VDL
GND
VDL
GND
C43 0.1F
R31 1k
R20 1k
R21 1k
R24 1k
R30 1k
R29 50
GND
J2
GND VDL
GND
1
1Y
U5
2Y 3Y
2 4 5 9
10
3
6
7 8
11
14
12 13
74VCX86
ENCX
1
B
1
A
2
B
2
A
3
B
3
A
4
B
4
A
DR
LATCH BYPASSING
4Y
SCHEMATIC SHOWS TWO GATE DELAY SETUP. FOR ONE DELAY, REMOVE R22 AND R37 AND ATTACH Rx (Rx = 0).
Figure 50. LFCSP Evaluation Board Schematic, Clock Input