Datasheet
AD9235 Data Sheet
Rev. D | Page 32 of 40
CLOCK TIMING ADJUSTMENTS
FOR A BUFFERED ENCODE USE R28
FOR A DIRECT ENCODE USE R27
GND
ENCX
ENC
R32
1kΩ
R37
25Ω
R23
0Ω
R22
0Ω
Rx
DNP
R28
0Ω
E50
E51
ENC
CLK
VDL
GND
GND
VDL
GND
PWR
C43
0.1µF
R31
1k
Ω
R30
1kΩ
R29
50
Ω
J2
GND
VDL
1Y
ENCX
1
2
1B
1A
DR
SCHEMATIC SHOWS TWO GATE DELAY SETUP
FOR ONE DELAY REMOVE R22 AND R37 AND
ATTACH Rx (Rx = 0Ω
)
C49
0.001µF
C48
0.001µF
C47
0.1µF
C1
0.1µF
C39
0.001µ
F
C38
0.001µF
C36
0.1µF
C34
0.1µF
C31
0.1µF
C30
0.001µF
C2
22µF
DRVDD
GND
C37
0.1
µF
C40
0.001
µF
C20
10µF
VDL
GND
C46
10µ
F
VAMP
GND
GND
C14
0.001µF
C41
0.1µF
C33
0.1µF
AVDD
DIGITAL BYPASSING
ANALOG BYPASSING
DUT BYPASSING
LATCH BYPASSING
C32
0.001µ
F
C25
10µF
C3
10µF
C4
10
µF
C10
22µF
2Y
4
5
2B
2A
3Y
9
10
3B
3A
4Y
12
13
3
6
7
8
11
14
4B
4A
CLKAT/DAC
R20
1k
Ω
E52
E53
VDL
GND
R21
1k
Ω
E31
E35
VDL GND
R24
1k
Ω
E43
E44
VDL
GND
R27
0Ω
GND
VDL DRVDD
AVDD
02461-056
ENCODE
GND
74VCX86
+
+
++++
Figure 56. LFCSP Evaluation Board Schematic, Clock Input