Datasheet

AD9233
Rev. A | Page 4 of 44
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS enabled, unless otherwise noted.
Table 1.
AD9233BCPZ-80 AD9233BCPZ-105 AD9233BCPZ-125
Parameter Tem p Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full 12 12 12 Bits
ACCURACY
No Missing Codes Full Guaranteed Guaranteed Guaranteed
Offset Error Full ±0.3 ±0.5 ±0.3 ±0.8 ±0.3 ±0.8 % FSR
Gain Error Full ±0.2 ±4.7 ±0.2 ±4.9 ±0.2 ±3.9 % FSR
Differential Nonlinearity (DNL)
1
Full ±0.3 ±0.5 ±0.5 LSB
25°C ±0.2 ±0.2 ±0.2 LSB
Integral Nonlinearity (INL)
1
Full ±1.2 ±1.2 ±1.2 LSB
25°C ±0.5 ±0.5 ±0.5 LSB
TEMPERATURE DRIFT
Offset Error Full ±15 ±15 ±15 ppm/°C
Gain Error Full ±95 ±95 ±95 ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode) Full ±5 ±20 ±5 ±35 ±5 ±35 mV
Load Regulation @ 1.0 mA Full 7 7 7 mV
INPUT REFERRED NOISE
VREF = 1.0 V 25°C 0.34 0.34 0.34 LSB rms
ANALOG INPUT
Input Span, VREF = 1.0 V Full 2 2 2 V p-p
Input Capacitance
2
Full 8 8 8 pF
REFERENCE INPUT RESISTANCE Full 6 6 6 kΩ
POWER SUPPLIES
Supply Voltage
AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
DRVDD Full 1.7 3.3 3.6 1.7 3.3 3.6 1.7 3.3 3.6 V
Supply Current
IAVDD
1
Full 138 155 178 194 220 236 mA
IDRVDD
1
(DRVDD = 1.8 V) Full 7 8 10 mA
IDRVDD
1
(DRVDD = 3.3 V) Full 12 14 17 mA
POWER CONSUMPTION
DC Input Full 248 279 320 350 395 425 mW
Sine Wave Input
1
(DRVDD = 1.8 V) Full 261 335 415 mW
Sine Wave Input
1
(DRVDD = 3.3 V) Full 288 365 452 mW
Standby
3
Full 40 40 40 mW
Power-Down Full 1.8 1.8 1.8 mW
1
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
2
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.
3
Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND).