Datasheet

AD9233
Rev. A | Page 34 of 44
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
NC7WZ07 A1 GND A2
Y1
VCC
Y2
NC7WZ16 A1 GND A2
Y1
VCC
Y2
RC0603
Optional
+5V=PROGRAMMING ONLY=AMPVDD
SPI CIRCUITRY
GP0
PICVCC
GP1
For FIFO controlled port, populate R555, R556, R557. When using PICSPI controlled port, populate R545, R546, R547.
REMOVE WHEN USING OR PROGRAMMING PIC (U506)
When using PICSPI controlled port, remove R555, R556, R557.
MCLR-GP3
+3.3V=NORMAL OPERATION=AVDD_3P3V
1
10
2
34
56
78
9
J504
PIC-HEADER
2
4
1
3
7 6 5
3 2
81
4
U506
R547 4.7K DNI
1 3 25
6 4
U507
1 3 25
6 4
U508
R548 10K
R549 10K
1K R552
SDIO_ODM
CSB_DUT SCLK_DTP
R553 1K
R551 1K
R550 10K
13
2
JP509
AVDD_3P3V
R554
0
R546 4.7K DNI
4.7K R545
DNI
C557
0.1UF
12
R559 261
R558 4.7K
21
D505
E504
R557
0
R556
0
R555
0
SDO_CHA
CSB1_CHA
SDI_CHA
SCLK_CHA
AVDD_3P3V
DUTAVDD
DNI
DNI
S1
DNI
DNI
DNI
DNI
DNI
HEADER UP MALE
RC 0603
CC0603
RC 060 3
DDVPMAV3P3_DDVA
DNI
PICVCC
GP1
GP0
MC LR-GP3
SOIC8
GP5 GP4
GP0 GP2 GP1 VSSVDD
MCLR
PIC12F629
0
5492-056
Figure 63. Evaluation Board Schematic, SPI Circuitry