Datasheet

AD9233
Rev. A | Page 25 of 44
Table 15. Memory Map Register
Addr
(Hex)
Parameter
Name
Bit 7
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
Chip Configuration Registers
00 chip_port_config 0 LSB
First
0 = Off
(Default)
1 = On
Soft
Reset
0 = Off
(Default)
1 = On
1 1 Soft
Reset
0 = Off
(Default)
1 = On
LSB
First
0 = Off
(Default)
1 = On
0 0x18 The nibbles
should be
mirrored. See
Interfacing to
High Speed
ADCs via SPI
User Manual
.
01 chip_id 8-Bit Chip ID Bits 7:0
(AD9233 = 0x00), (Default)
Read-
Only
Default is
unique chip ID,
different for
each device.
02 chip_grade Open Open Open Open Child ID
0 =
125
MSPS,
1 =
105
MSPS
Open Open Open Read-
Only
Child ID used
to differentiate
speed grades.
Device Index and Transfer Registers
FF device_update Open Open Open Open Open Open Open SW Transfer 0x00 Synchronously
transfers data
from the
master
shift register to
the slave.
Global ADC Functions
08 modes Open Open PDWN
0—Full
1—
Standby
Open Open Internal Power-Down Mode
000—Normal (Power-Up)
001—Full Power-Down
010—Standby
011—Normal (Power-Up)
Note: External PDWN pin
overrides this setting.
0x00 Determines
various generic
modes of chip
operation. See
Power
Dissipation
and Standby
Mode
and
SPI-Accessible
Features
sections.
09 clock Open Open Open Open Open Open Open Duty Cycle
Stabilizer
0—
Disabled
1—Enabled
0x01 See
Clock Duty
Cycle
and
SPI-Accessible
Features
sections.
Flexible ADC Functions
10 offset
Digital Offset Adjust <5:0>
011111
011110
011101
…
000010
000001
000000
111111
111110
111101
...
100001
100000
Offset in LSBs
+7 3/4
+7 1/2
+7 1/4
+1/2
+1/4
0
−1/4
−1/2
−3/4
−7 3/4
−8
0x00 Adjustable for
offset inherent
in the
converter.
See
SPI-
Accessible
Features
section.