Datasheet

AD9233
Rev. A | Page 20 of 44
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD9233. Power
supplies for clock drivers should be separated from the ADC
output driver supplies to avoid modulating the clock signal with
digital noise. The power supplies should also not be shared with
analog input circuits such as buffers to avoid the clock
modulating onto the input signal or vice versa. Low jitter,
crystal-controlled oscillators make the best clock sources.
If the clock is generated from another type of source (by
gating, dividing, or other methods), it should be retimed by the
original clock at the last step.
Refer to Application Notes
AN-501, Aperture Uncertainty and
ADC System Performance, and
AN-756, Sampled Systems and
the Effects of Clock Phase Noise and Jitter for more in-depth
information about jitter performance as it relates to ADCs.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 52 and Figure 53, the power dissipated by
the AD9233 is proportional to its sample rate. The digital power
dissipation is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current (I
DRVDD
) can be calculated as
N
f
CVI
CLK
LOAD
DRVDDDRVDD
×××=
2
where N is the number of output bits (12 in the case of the
AD9233).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency, f
CLK
/2. In practice, the DRVDD current is
established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal. Reducing the capacitive load
presented to the output drivers can minimize digital power
consumption.
The data used for
Figure 52 and Figure 53 is based on the
same operating conditions as used in the plots in the
Typical
Performance Characteristics
section with a 5 pF load on each
output driver.
475
325
0 125
CLOCK FREQUENCY (MSPS)
POWER (mW)
450
425
400
375
350
250
0
CURRENT (mA)
200
150
100
50
25 50 75 100
IDRVDD
IAVDD
TOTAL POWER
05492-034
Figure 52. AD9233-125 Power and Current vs. Clock Frequency, F
IN
= 30 MHz
410
250
5
CLOCK FREQUENCY (MSPS)
POWER (mW)
200
180
0
CURRENT (mA)
160
140
120
100
80
60
40
20
30 55 80 105
390
370
350
330
310
290
270
IDRVDD
IAVDD
TOTAL POWER
05492-082
Figure 53. AD9233-105 Power and Current vs. Clock Frequency, F
IN
= 30 MHz
290
215
0
CLOCK FREQUENCY (MSPS)
POWER (mW)
150
0
CURRENT (mA)
120
90
60
30
80
IDRVDD
IAVDD
TOTAL POWER
05492-093
275
260
245
230
20 40 60
Figure 54. AD9233-80 Power and Current vs. Clock Frequency, F
IN
= 30 MHz