Datasheet

AD9233
Rev. A | Page 18 of 44
Table 9. Reference Configuration Summary
Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p)
External Reference AVDD N/A 2 × External Reference
Internal Fixed Reference VREF 0.5 1.0
Programmable Reference 0.2 V to VREF 0.5 × (1 + R2/R1) (See Figure 43) 2 × VREF
Internal Fixed Reference AGND to 0.2 V 1.0 2.0
0
–1.25
02
LOAD CURRENT (mA)
REFERENCE VOLTAGE ERROR (%)
.0
–0.25
–0.50
–0.75
–1.00
0.5 1.0 1.5
VREF = 0.5V
VREF = 1V
05492-032
Figure 44. VREF Accuracy vs. Load
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift
characteristics.
Figure 45 shows the typical drift characteristics
of the internal reference in both 1 V and 0.5 V modes.
–40
–20
10
0
TEMPERATURE (°C)
REFERENCE VOLTAGE ERROR (mV)
8
6
4
2
80
0 204060
VREF = 0.5V
VREF = 1V
05492-033
Figure 45. Typical VREF Drift
When the SENSE pin is tied to the AVDD pin, the internal
reference is disabled, allowing the use of an external reference.
An internal resistor divider loads the external reference with an
equivalent 6 kΩ load (see
Figure 11). In addition, an internal
buffer generates the positive and negative full-scale references
for the ADC core. Therefore, the external reference must be
limited to a maximum of 1 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9233 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ pin and the
CLK− pin via a transformer or capacitors. These pins are biased
internally (see
Figure 5) and require no external bias.
Clock Input Options
The AD9233 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal used, the jitter of the clock
source is of the most concern, as described in the
Jitter
Considerations
section.
Figure 46 shows one preferred method for clocking the
AD9233. A low jitter clock source is converted from single-
ended to a differential signal using an RF transformer. The
back-to-back Schottky diodes across the transformer secondary
limit clock excursions into the AD9233 to approximately
0.8 V p-p differential. This helps prevent the large voltage
swings of the clock from feeding through to other portions of
the AD9233 while preserving the fast rise and fall times of the
signal, which are critical to a low jitter performance.
05492-048
0.1µF
0.1µF
0.1µF0.1µF
SCHOTTKY
DIODES:
HSMS2812
CLOCK
INPUT
50Ω
100Ω
CLK–
CLK+
ADC
AD9233
MIN-CIRCUITS
ADT1–1WT, 1:1Z
XFMR
Figure 46. Transformer Coupled Differential Clock
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins, as shown in
Figure 47. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515 family of clock drivers offers
excellent jitter performance.
CLOCK
INPUT
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
240Ω240Ω
CLOCK
INPUT
05492-049
PECL DRIVER
50Ω* 50Ω*
CLK
CLK
*50Ω RESISTORS ARE OPTIONAL
CLK–
CLK+
ADC
AD9233
AD951x
Figure 47. Differential PECL Sample Clock