Datasheet

AD9230
Rev. 0 | Page 7 of 32
TIMING DIAGRAMS
N – 1
N
N + 2
N + 3
N + 4
N + 5
N + 1
CLK+
N – 7 N – 6 N – 5 N – 4 N – 3
CLK–
DCO+
DCO–
DX+
DX–
VIN
t
A
t
CH
t
CL
1/ f
S
t
CPD
t
SKEW
t
PD
06002-002
Figure 2. Single Data Rate Mode
N – 1
N
N + 2
N + 3
N + 4
N + 5
N + 1
CLK+
CLK–
DCO+
DCO–
D6
N – 8
D0
N – 7
D6
N – 7
D0
N – 6
D6
N – 6
D0
N – 5
D6
N – 5
D0
N – 4
D6
N – 4
D0
N – 3
D0/D6+
D0/D6–
D11
N – 8
D5
N – 7
D11
N – 7
D5
N – 6
D11
N – 6
D5
N – 5
D11
N – 5
D5
N – 4
D11
N – 4
D5
N – 3
D5/D11+
D5/D11–
VIN
t
A
t
CH
t
CL
1/ f
S
t
CPD
t
SKEW
t
PD
06002-003
6 MSBs
6 LSBs
Figure 3. Double Data Rate Mode