Datasheet

AD9230
Rev. 0 | Page 28 of 32
Addr.
(Hex)
Parameter Name
Bit 7
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Def.
Value
(Hex)
Default Notes/
Comments
ADC Functions
08 modes 0 0 PDWN:
0 = full
(default)
1 =
standby
0 0 Internal power-down mode:
000 = normal (power-up,
default)
001 = full power-down
010 = standby
011 = normal (power-up)
Note: External PDWN pin
overrides this setting.
0x00 Determines
various generic
modes of chip
operation.
09 clock 0 0 0 0 0 0 0 Duty
cycle
stabilizer:
0 =
disabled
1 =
enabled
(default)
0x01
OD test_io Reset
PN23
gen:
1 = on
0 = off
(default)
Reset
PN9 gen:
1 = on
0 = off
(default)
Output test mode:
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checker board output
0101 = PN 23 sequence
0110 = PN 9
0111 = one/zero word toggle
1000 = unused
1001 = unused
1010 = unused
1011 = unused
1100 = unused
(Format determined by output_mode)
0x00 When set, the
test data is
placed on the
output pins in
place of normal
data.
OF ain_config 0 0 0 0 0 Analog
input
disable:
1 = on
0 = off
(default)
CML
enable:
1 = on
0 = off
(default)
0 0x00
14 output_mode 0 0 Output
enable:
0 =
enable
(default)
1 =
disable
DDR:
1 =
enabled
0 =
disabled
(default)
Output
invert:
1 = on
0 = off
(default)
Data format select:
00 = offset binary
(default)
01 = twos
complement
10 = Gray code
0x00 0
15 output_adjust 0 0 LVDS
course
adjust:
0 =
3.5 mA
(default)
1 =
2.0 mA
LVDS fine adjust:
001 = 3.50 mA
010 = 3.25 mA
011 = 3.00 mA
100 = 2.75 mA
101 = 2.50 mA
110 = 2.25 mA
111 = 2.00 mA
0x00 0
16 output_phase Output
clock
polarity
1 =
inverted
0 =
normal
(default)
0 0 0 0x03