Datasheet
AD9230
Rev. 0 | Page 11 of 32
DNC = DO NOT CONNECT
PIN 1
INDICATOR
1D3/D9–
2D3/D9+
3D4/D10–
4D4/D10+
5(MSB) D5/D11–
6(MSB) D5/D11
+
7DRVDD
8DRGND
9OR–
10OR+
11DNC
12DNC
13DNC
14DNC
35 VIN+
36 VIN–
37 AVDD
38 AVDD
39 AVDD
40 CML
41 AVDD
42 AVDD
34 AVDD
33 AVDD
32 AVDD
31 RBIAS
30 AVDD
29 PWDN
15
DNC
16
DNC
17
DNC
19
DNC
21
DNC
/(OR–)
20
DNC
22
DNC/(OR+)
23
DRGND
24
DRVDD
25
SDIO/DCS
26
SCLK/DFS
27
CSB
28
RESET
18
DNC
45
C
LK–
46
AVDD
47
DRVDD
48
DRGND
49
DCO–
50
D
CO+
51
D0/D6– (LSB)
52
D0/D6+ (LSB)
53
D1/D7–
54
D1/D7+
44
CLK+
43
AVDD
TOP VIEW
(Not to Scale)
PIN 0 (EXPOSED PADDLE) = AGND
AD9230
55
D2/D8–
56
D2/D8+
06002-005
Figure 5. Double Data Rate
Table 8. Double Data Rate Mode Pin Function Descriptions
Pin No. Mnemonic Description
30, 32 to 34, 37 to 39,
41 to 43, 46
AVDD 1.8 V Analog Supply.
7, 24, 47 DRVDD 1.8 V Digital Output Supply.
0 AGND
1
Analog Ground.
8, 23, 48 DRGND
1
Digital Output Ground.
35 VIN+ Analog Input—True.
36 VIN− Analog Input—Complement.
40 CML
Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the
optimized internal bias voltage for VIN+/VIN−.
44 CLK+ Clock Input—True.
45 CLK− Clock Input—Complement.
31 RBIAS Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.) Nominally 0.5 V.
28 RESET CMOS-Compatible Chip Reset (Active Low).
25 SDIO/DCS
Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select
(External Pin Mode).
26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode).
27 CSB Serial Port Chip Select (Active Low).
29 PWDN Chip Power-Down.
49 DCO− Data Clock Output—Complement.
50 DCO+ Data Clock Output—True.
51 D0/D6− D0/D6 Complement Output Bit (LSB).
52 D0/D6+ D0/D6 True Output Bit (LSB).
53 D1/D7− D1/D7 Complement Output Bit.
54 D1/D7+ D1/D7 True Output Bit.
55 D2/D8− D2/D8 Complement Output Bit.
56 D2/D8+ D2/D8 True Output Bit.
1 D3/D9− D3/D9 Complement Output Bit.
2 D3/D9+ D3/D9 True Output Bit.
3 D4/D10− D4/D10 Complement Output Bit.
4 D4/D10+ D4/D10 True Output Bit.
5 D5/D11− D5/D11 Complement Output Bit (MSB).
6 D5/D11+ D5/D11 True Output Bit (MSB).