Datasheet

AD9229
Rev. B | Page 5 of 40
DIGITAL SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 3.
AD9229-50 AD9229-65
Parameter Temperature
Test
Level
Min Typ Max Min Typ Max Unit
CLOCK INPUT
Logic Compliance TTL/CMOS TTL/CMOS
High Level Input Voltage Full IV 2.0 2.0 V
Low Level Input Voltage Full IV 0.8 0.8 V
High Level Input Current Full VI 0.5 ±10 0.5 ±10 µA
Low Level Input Current Full VI 0.5 ±10 0.5 ±10 µA
Input Capacitance 25°C V 2 2 pF
LOGIC INPUTS (PDWN)
Logic 1 Voltage Full IV 2.0 2.0 V
Logic 0 Voltage Full IV 0.8 0.8 V
High Level Input Current Full IV 0.5 ±10 0.5 ±10 µA
Low Level Input Current Full IV 0.5 ±10 0.5 ±10 µA
Input Capacitance 25°C V 2 2 pF
DIGITAL OUTPUTS (D+, D–)
Logic Compliance LVDS LVDS
Differential Output Voltage Full VI 260 440 260 440 mV
Output Offset Voltage Full VI 1.15 1.25 1.35 1.15 1.25 1.35 V
Output Coding Full VI
Offset
binary
Offset
binary