Datasheet

Data Sheet AD9228
Rev. E | Page 41 of 56
CSB
C217
0.1µF
C220
0.1µF
C221
0.1µF
C218
0.1µF
C219
0.1µF
C223
0.1µF
C222
0.1µF
AVDD_3.3V
CLK CLKB
GND
GND_PAD
OUT0
OUT0B
OUT1
OUT1B
RSET
S0
S1
S10
S2
S3
S4
S5
S6
S7
S8
S9
SYNCB
VREF
VS
SIGNAL=DNC;27,28
INPUT ENCODE ENC ENC DNP
CLOCK CIRCUIT
OPTIONAL CLOCK DRIVE CIRCUIT
DISABLE ENABLE
OPTIONAL CLOCK
OSCILLATOR
C224
0.1µF
R214 10kΩ R215 10kΩ
14
78 1 3 5
12 10
OSC201
VFAC3H-L
C207
0.1µF
DNP
C208
0.1µF
DNP
C209
0.1µF
DNP
C215
0.1µF
DNP
C211
0.1µF
C210
0.1µF
E202
1
E201
P201 P203
AVDD_3.3V
12
6
7
25
8
16
9
15
10
14
11
13
18 19 23 22
32
1
31
33
U202
SIGNAL=AVDD_3.3V;4,17,20,21,24,26,29,30
AD9515
3
2
1
CR201
HSMS2812
R220
DNP
R240 243Ω
R243 100Ω
R241 243Ω
R242
100Ω
6 5 43
2 1
T201
1
2
3
J205
C205
0.1µF
C216
0.1µF
R213 49.9kΩ R216 0Ω
R221
10kΩ
R212 0Ω DNP
R219
DNP
S0S1S2S3S4S5S6S7S8S9S10
OPT_CLK OPT_CLK
CLK
AVDD_3.3V
OPT_CLK
OPT_CLK
CLK CLK
LVPECL OUTPUT LVDS OUTPUT
CLK
AVDD_3.3V
1 1
E203
AVDD_3.3V
VCC
GNDOUT
OE
OE'
GND'
VCC'
OUT'
R244
DNP
R245
0Ω
S4 S0 S5 S3 S2 S1
AVDD_3.3V AVDD_3.3V AVDD_3.3V AVDD_3.3V AVDD_3.3V AVDD_3.3V
R246
DNP
R247
0Ω
R248
DNP
R249
0Ω
R250
DNP
R251
0Ω
R252
DNP
R253
0Ω
R254
DNP
R255
0Ω
R256
DNP
R257
0Ω
S10
S6 S9 S8 S7
AVDD_3.3V AVDD_3.3V AVDD_3.3V AVDD_3.3V AVDD_3.3V
R258
DNP
R259
0Ω
R260
DNP
R261
0Ω
R262
DNP
R263
0Ω
R264
DNP
R265
0Ω
A1 A2 A3 A4 A5 A6 A7 A8 A9
GNDAB1
GNDAB10
GNDAB2 GNDAB3 GNDAB4 GNDAB5 GNDAB6 GNDAB7 GNDAB8 GNDAB9 GNDCD1
GNDCD10
GNDCD2 GNDCD3 GNDCD4 GNDCD5 GNDCD6 GNDCD7 GNDCD8 GNDCD9
HEADER 6469169-1
R205–R211 OPTIONAL OUTPUT TERMINATIONS
DIGITAL OUTPUTS
CSB3__CHB
SDI_CHB
SDO_CHA CSB2_CHA CSB1_CHA SDI_CHA SCLK_CHA
R206 DNP R211 DNP R210 DNP R209 DNP R208 DNP
P202
R207 DNP
SCLK_CHB
DCO
C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C10
50 49 48 47 46 45 44 43 42 41 20 19 18 17 16 15 14 13 12
D10
D9 D8 D7 D6 D5 D4 D3 D2 D1
B10
B9 B8 B7 B6 B5 B4 B3 B2 B1
11
CHD CHC CHB CHA FCO
DCO
CHD CHC CHB CHA
FCO
SDO_CHB
CSB4_CHB
40 60
1 9
21 22
4 5
25
6
26
8
31 32 33 34
35 36
37 38 29 10 30
2
23
3
24 28 51 52 53 54 55 56 57 58 39 59
7
27
ODM ENABLE
CLK
AVDD CLK+ CLK–
D + A
D + B
D + C
D + D
D – A
D – B
D – C
D – D
DCO+
DCO–
DRVDD DRGND
FCO+
FCO–
PDWN
RBIAS
REFB
REFT
SCLK/DTP
SDIO/ODM
SENSE
VIN + A
VIN + B
VIN + C
VIN + D
VIN – A
VIN – B
VIN – C
VIN – D
VREF
AVDD AVDD AVDD AVDD AVDD
AVDD
AVDD AVDD AVDD AVDD
AVDD
AVDD
DRGND
DRVDD
REFERENCE DECOUPLING
C204
0.1µF
C203 0.1µF
C202 2.2µF
C201
0.1µF
R205
10kΩ
R203
100kΩ
R204
100kΩ
3
2
1
J201
1 8 730
20
18
16
14
19
17
15
13
24
23
11 12
22
21
10
2
25 26 27 32 35 36
39
45
46
5 6 9
31
40
43
44
28 29
41
33
38
47
4
34
37
48
3
42
U201
AD9228LFCSP
R202 100kΩ
CSB_DUT
1
2
3
J202
SDIO_ODM
1
2
3
J
2
0
3
S
C
L
K
_
D
T
P
3
2
1
J
2
0
4
D
R
V
D
D
_
D
U
T
D
R
V
D
D
_
D
U
T
R
2
0
1
1
0
k
Ω
AVDD_DUT
CHA
CHB
CHC
CHD
CHA
CHB
CHC
DCO
DCO
FCO
FCO
A
V
D
D
_
D
U
T
A
V
D
D
_
D
U
T
A
V
D
D
_
D
U
T
AVDD_DUT
AVDD_DUT
VSENSE_DUT
V
I
N
_
A
VIN_B
VIN_C
V
I
N
_
A
VIN_B
VREF_DUT
A
V
D
D
_
D
U
T
A
V
D
D
_
D
U
T
C
L
K
CHD
A
V
D
D
_
D
U
T
A
V
D
D
_
D
U
T
A
V
D
D
_
D
U
T
A
V
D
D
_
D
U
T
A
V
D
D
_
D
U
T
V
I
N
_
D
VIN_C
V
I
N
_
D
G
N
D
G
N
D
A
V
D
D
_
D
U
T
P
W
D
N
E
N
A
B
L
E
A
L
W
A
Y
S
E
N
A
B
L
E
S
P
I
D
T
P
E
N
A
B
L
E
U
2
0
3
CW
V
R
E
F
=
1
V
V
R
E
F
=
E
X
T
E
R
N
A
L
V
R
E
F
=
0
.
5
V
R
E
M
O
V
E
C
2
1
4
W
H
E
N
U
S
I
N
G
E
X
T
E
R
N
A
L
V
R
E
F
V
R
E
F
=
0
.
5
V
(
1
+
R
2
3
2
/
R
2
3
3
)
V
R
E
F
S
E
L
E
C
T
R
E
F
E
R
E
N
C
E
C
I
R
C
U
I
T
C
2
1
2
0
.
1
µ
F
R
2
2
9
4
.
9
9
k
Ω
C
2
1
4
1
µ
F
C
2
1
3
0
.
1
µ
F
R
2
3
0
1
0
k
Ω
R
2
3
1
D
N
P
D
N
P
V
S
E
N
S
E
_
D
U
T
R
2
2
8
4
7
0
k
Ω
D
N
P
D
N
P
R
2
3
4
D
N
P
R
2
3
5
D
N
P
R
2
3
6
D
N
P
R
2
3
7
0
Ω
D
N
P
A
V
D
D
_
D
U
T
V
R
E
F
_
D
U
T
AVDD_DUT
T
R
I
M
/
N
C
V–
V
+
A
D
R
5
1
0
1
V
R
2
3
2
D
N
P
R
2
3
3
D
N
P
R
2
1
7
0
Ω
R
2
1
8
0
Ω
R
2
2
5
0
Ω
D
N
P
R
2
2
6
4
9
.
9
Ω
D
N
P
R
2
2
7
0
Ω
D
N
P
R
2
3
8
D
N
P
R
2
3
9
1
0
k
Ω
C
2
0
6
0
.
1
µ
F
R
2
2
3
0
Ω
R
2
2
4
0
Ω
R
2
2
2
4
.
1
2
k
Ω
05727-016
2
3
5
N
C
=
N
O
C
O
N
N
E
C
T
R266
100kΩ - DNP
R267
100kΩ - DNP
C
L
I
P
S
I
N
E
O
U
T
(
D
E
F
A
U
L
T
)
D
N
P
:
D
O
N
O
T
P
O
P
U
L
A
T
E
O
P
T
I
O
N
A
L
E
X
T
R
E
F
Figure 74. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface