Datasheet

AD9228 Data Sheet
Rev. E | Page 24 of 56
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (f
A
)
due only to aperture jitter (t
J
) can be calculated by
SNR Degradation = 20 × log 10(1/2 × π × f
A
× t
J
)
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 57).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9228.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators are
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or another method), it
should be retimed by the original clock during the last step.
Refer to the AN-501 Application Note and to the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs.
1 10 100 1000
05727-038
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
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100
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130
0.125 ps
0.25 ps
0.5 ps
1.0 ps
2.0 ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
RMS CLOCK JITTER REQUIREMENT
SNR (dB)
Figure 57. Ideal SNR vs. Input Frequency and Jitter
Power Dissipation and Power-Down Mode
As shown in Figure 58 and Figure 59, the power dissipated by
the AD9228 is proportional to its sample rate. The digital power
dissipation does not vary significantly because it is determined
primarily by the DRVDD supply and bias current of the LVDS
output drivers.
10 2015 30 3525 40
CURRENT (mA)
ENCODE (MSPS)
0
5727-089
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260
280
0
20
40
100
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DRVDD CURRENT
TOTAL POWER
AVDD CURRENT
POWER (mW)
Figure 58. Supply Current vs. f
SAMPLE
for f
IN
= 10.3 MHz, f
SAMPLE
= 40 MSPS
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CURRENT (mA)
POWER (mW)
ENCODE (MSPS)
05727-081
0
50
100
150
200
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300
340
320
360
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460
480
DRVDD CURRENT
TOTAL POWER
AVDD CURRENT
Figure 59. Supply Current vs. f
SAMPLE
for f
IN
= 10.3 MHz, f
SAMPLE
= 65 MSPS