Datasheet

Data Sheet AD9228
Rev. E | Page 11 of 56
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIN + A
VIN – A
AVDD
VIN + D
VIN – D
DRVDD
DRGND
CLK+
CLK–
AVDD
DRVDD
DRGND
AVDD
AVDD
CSB
SCLK/DTP
SDIO/ODM
PDWN
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
D + A
D – A
D + B
D – B
D + C
D – C
D + D
D – D
DCO+
DCO–
FCO+
FCO–
VIN + B VIN – B VIN + C
VIN –
C
AVDD REFT REFB VREF SENSE AVDD AVDD RBIAS
11
12
10
9
8
7
6
5
4
3
2
1
25
24
26
27
28
29
30
31
32
33
34
35
36
22 21 23 20 19 18 17 16 15 14 13
37 38 39 40 41 42 43 44 45 46 47 48
05727-003
PIN 1
INDICATOR
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
AD9228
TOP VIEW
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.
Figure 5. 48-Lead LFCSP Pin Configuration, Top View
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
0 AGND Analog Ground (Exposed Paddle)
1, 2, 5, 6, 9, 10, 27, 32,
35, 36, 39, 45, 46
AVDD 1.8 V Analog Supply
11, 26 DRGND Digital Output Driver Ground
12, 25 DRVDD 1.8 V Digital Output Driver Supply
3 VIN − D ADC D Analog Input Complement
4 VIN + D ADC D Analog Input True
7 CLK− Input Clock Complement
8 CLK+ Input Clock True
13 D − D ADC D Digital Output Complement
14 D + D ADC D Digital Output True
15 D − C ADC C Digital Output Complement
16 D + C ADC C Digital Output True
17 D − B ADC B Digital Output Complement
18 D + B ADC B Digital Output True
19 D − A ADC A Digital Output Complement
20 D + A ADC A Digital Output True
21 FCO− Frame Clock Output Complement
22 FCO+ Frame Clock Output True
23 DCO− Data Clock Output Complement
24 DCO+ Data Clock Output True
28 SCLK/DTP Serial Clock/Digital Test Pattern
29 SDIO/ODM Serial Data IO/Output Driver Mode
30 CSB Chip Select Bar
31 PDWN Power-Down