Datasheet

AD9216
Rev. A | Page 6 of 40
SWITCHING SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; A
IN
= −0.5 dBFS differential input, 1.0 V internal reference,
T
MIN
to T
MAX
, DCS enabled, unless otherwise noted.
Table 4.
AD9216BCPZ-65 AD9216BCPZ-80 AD9216BCPZ-105
Parameter Temp Test Level Min Typ Max Min Typ Max Min Typ Max Unit
SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 65 80 105 MSPS
Minimum Conversion Rate Full IV 10 10 10 MSPS
CLK Period Full VI 15.4 12.5 9.5 nS
CLK Pulse Width High Full VI 4.6 4.4 3.8 nS
CLK Pulse Width Low Full VI 4.6 4.4 3.8 nS
OUTPUT PARAMETERS
1
Output Propagation Delay
2
(t
PD
) 25°C I 4.5 6.4 4.5 6.4 4.5 6.4 nS
Valid Time
3
(t
V
) 25°C I 2.0 2.0 2.0
Output Rise Time (10% to 90%) 25°C V 1.0 1.0 1.0 nS
Output Fall Time (10% to 90%) 25°C V 1.0 1.0 1.0 nS
Output Enable Time
4
Full IV 1 1 1 Cycle
Output Disable Time
4
Full IV 1 1 1 Cycle
Pipeline Delay (Latency) Full IV 6 6 6 Cycle
APERTURE
Aperture Delay (t
A
) 25°C V 1.5 1.5 1.5 nS
Aperture Uncertainty (t
J
) 25°C V 0.5 0.5 0.5 pS
rms
Wake-Up Time
5
25°C V 7 7 7 ms
OUT-OF-RANGE RECOVERY TIME 25°C V 1 1 1 Cycle
1
C
LOAD
equals 5 pF maximum for all output switching parameters.
2
Output delay is measured from clock 50% transition to data 50% transition.
3
Valid time is approximately equal to the minimum output propagation delay.
4
Output enable time is OEB_A, OEB_B falling to respective channel outputs coming out of high impedance. Output disable time is OEB_A, OEB_B rising to respective
channel outputs going into high impedance.
5
Wake-up time is dependent on value of decoupling capacitors; typical values shown for 0.1 µF and 10 µF capacitors on REFT and REFB.