Datasheet

AD9216
Rev. A | Page 10 of 40
Pin No. Mnemonic Description
46 to 51,
54 to 57
D0_A (LSB) to
D9_A (MSB)
Channel A Data Output Bits.
59 OEB_A Output Enable for Channel A.
Logic 0 enables Data Bus A.
Logic 1 sets outputs to High-Z.
60 PDWN_A Power-Down Function Selection for Channel A.
Logic 0 enables Channel A.
Logic 1 powers down Channel A. (Outputs static, not High-Z.)
61 MUX_SELECT Data Multiplexed Mode. (See Data Format section for how to enable.)
62 SHARED_REF Shared Reference Control Bit. Low for independent reference mode; high for shared reference mode.
63 CLK_A Clock Input Pin for Channel A.
1
It is recommended that all ground pins (AGND and DRGND) be tied to a common ground plane.