Datasheet

Data Sheet AD9215
Rev. B | Page 5 of 36
Table 3. Digital Specifications
AD9215BRU-65/
AD9215BCP-65
AD9215BRU-80/
AD9215BCP-80
AD9215BRU-105/
AD9215BCP-105
Parameter Temp
Test
Level Min Typ Max Min Typ Max Min Typ Max Unit
LOGIC INPUTS (CLK, PDWN)
High Level Input Voltage Full IV 2.0 2.0 2.0 V
Low Level Input Voltage Full IV 0.8 0.8 0.8 V
High Level Input Current
Full
IV
−650
+10
−650
+10
−650
+10
µA
Low Level Input Current Full IV −70 +10 −70 +10 −70 +10 µA
Input Capacitance Full V 2 2 2 pF
LOGIC OUTPUTS
1
DRVDD = 2.5 V
High Level Output Voltage Full IV 2.45 2.45 2.45 V
Low Level Output Voltage Full IV 0.05 0.05 0.05 V
1
Output voltage levels measured with a 5 pF load on each output.
Table 4. Switching Specifications
AD9215BRU-65/
AD9215BCP-65
AD9215BRU-80/
AD9215BCP-80
AD9215BRU-105/
AD9215BCP-105
Parameter Temp
Test
Level Min Typ Max Min Typ Max Min Typ Max
Unit
CLOCK INPUT PARAMETERS
Maximum Conversion Rate Full VI 65 80 105 MSPS
Minimum Conversion Rate Full V 5 5 5 MSPS
CLOCK Period Full V 15.4 12.5 9.5 ns
DATA OUTPUT PARAMETERS
Output Delay
1
(t
OD
) Full VI 2.5 4.8 6.5 2.5 4.8 6.5 2.5 4.8 6.5 ns
Pipeline Delay (Latency) Full V 5 5 5 Cycles
Aperture Delay 25°C V 2.4 2.4 2.4 ns
Aperture Uncertainty (Jitter) 25°C V 0.5 0.5 0.5 ps rms
Wake-Up Time
2
25°C V 7 7 7 ms
OUT-OF-RANGE RECOVERY TIME 25°C V 1 1 1 Cycles
02874-A-002
t
A
t
PD
N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 N+2
ANALOG
INPUT
CLK
DATA
OUT
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
Figure 2. Timing Diagram
1
Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
2
Wake-up time is dependent on the value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.