Datasheet

AD9204
Rev. 0 | Page 8 of 36
TIMING SPECIFICATIONS
Table 5.
Parameter Conditions Min Typ Max Unit
SYNC TIMING REQUIREMENTS
t
SSYNC
SYNC to rising edge of CLK setup time 0.24 ns
t
HSYNC
SYNC to rising edge of CLK hold time 0.40 ns
SPI TIMING REQUIREMENTS
t
DS
Setup time between the data and the rising edge of SCLK 2 ns
t
DH
Hold time between the data and the rising edge of SCLK 2 ns
t
CLK
Period of the SCLK 40 ns
t
S
Setup time between CSB and SCLK 2 ns
t
H
Hold time between CSB and SCLK 2 ns
t
HIGH
SCLK pulse width high 10 ns
t
LOW
SCLK pulse width low 10 ns
t
EN_SDIO
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
10 ns
t
DIS_SDIO
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge
10 ns
SYNC
CLK+
t
HSYNC
t
SSYNC
08122-004
Figure 4. SYNC Input Timing Requirements