Datasheet
AD9204
Rev. 0 | Page 10 of 36
PIN 1
INDICATOR
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D6B
D7B
DRVDD
D8B
D9B (MSB)
ORB
DCOB
DCOA
NC
NC
NC
DRVDD
NC
NC
NC
D0A (LSB)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AVDD
AVDD
VIN+B
VIN–B
AVDD
AVDD
RBIAS
VCM
SENSE
VREF
AVDD
AVDD
VIN–A
VIN+A
AVDD
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK+
CLK–
SYNC
NC
NC
NC
NC
NC
NC
DRVDD
D0B (LSB)
D1B
D2B
D3B
D4B
D5B
PDWN
OEB
CSB
SCLK/DFS
SDIO/DCS
ORA
D9A (MSB)
D8A
D7A
D6A
D5A
DRVDD
D4A
D3A
D2A
D1A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9204
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND
TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL
STRENGTH BENEFITS.
08122-005
Figure 5. Pin Configuration
Table 8. Pin Function Description
Pin No. Mnemonic Description
0 GND Exposed paddle is the only ground connection for the chip. Must be connected to PCB AGND.
1, 2 CLK+, CLK− Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
3 SYNC Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.
4, 5, 6, 7, 8, 9, 25, 26, 27,
29, 30, 31
NC Do Not Connect.
10, 19, 28, 37 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V).
11 to 18, 20, 21 D0B to D9B Channel B Digital Outputs. D9B = MSB.
22 ORB Channel B Out-of-Range Digital Output.
23 DCOB Channel B Data Clock Digital Output.
24 DCOA Channel A Data Clock Digital Output.
32 to 36, 38 to 42 D0A to D9A Channel A Digital Outputs. D9A = MSB.
43 ORA Channel A Out-of-Range Digital Output.
44 SDIO/DCS
SPI Data Input/Output (SDIO). Bidirectional SPI Data I/O in SPI mode. 30 kΩ internal pull-
down in SPI mode.
Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode.
30 kΩ internal pull-up in non-SPI (DCS) mode.
45 SCLK/DFS SPI Clock (SCLK) Input in SPI mode. 30 kΩ internal pull-down.
Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal
pull-down.
DFS high = twos complement output.
DFS low = offset binary output.
46 CSB SPI Chip Select. Active low enable; 30 kΩ internal pull-up.
47 OEB
Digital Input. Enable Channel A and Channel B digital outputs if low, three-state outputs if
high. 30 kΩ internal pull-down.
48 PDWN Digital Input. 30 kΩ internal pull-down.
PDWN high = power-down device.
PDWN low = run device, normal operation.