Datasheet

AD9203
Rev. B | Page 4 of 28
Parameter Symbol Min Typ Max Unit Conditions
Two-Tone Intermodulation Distortion IMD 68 dB f = 44.49 MHz and 45.52 MHz
Differential Phase DP 0.2 Degree NTSC 40 IRE Ramp
Differential Gain DG 0.3 %
DIGITAL INPUTS
High Input Voltage V
IH
2.0 V
Low Input Voltage V
IL
0.4 V
Clock Pulse Width High 11.25 ns
Clock Pulse Width Low 11.25 ns
Clock Period
2
25 ns
DIGITAL OUTPUTS
High-Z Leakage I
OZ
± 5.0 µA Output = 0 to DRVDD
Data Valid Delay t
OD
5 ns C
L
= 20 pF
Data Enable Delay t
DEN
6 ns C
L
= 20 pF
Data High-Z Delay t
DHZ
6 ns C
L
= 20 pF
LOGIC OUTPUT (with DRVDD = 3 V)
High Level Output Voltage (I
OH
= 50 µA) V
OH
2.95 V
High Level Output Voltage (I
OH
= 0.5 mA) V
OH
2.80 V
Low Level Output Voltage (I
OL
= 1.6 mA) V
OL
0.3 V
Low Level Output Voltage (I
OL
= 50 µA) V
OL
0.05 V
1
Differential Input (2 V p-p).
2
The AD9203 will convert at clock rates as low as 20 kHz.
00573-002
N
N+1
N–1
N+2
N+3
N+4
N+5
N+6
A
NALOG
INPUT
DATA
OUT
N–7 N–6 N–5 N–4
T
OD
= 3ns MIN
7ns MAX
(C
LOAD
= 20pF)
N–3 N–2 N–1 N N+1
CLOCK
Figure 2. Timing Diagram