Datasheet

Data Sheet AD9148
Rev. B | Page 7 of 72
DIGITAL INPUT DATA TIMING SPECIFICATIONS
Table 3.
Parameter Min Typ Max Unit
LATENCY (DACCLK CYCLES)
1× Interpolation (with or Without Coarse Modulation) 64 Cycles
2× Interpolation (with or Without Coarse Modulation) 125 Cycles
4× Interpolation (with or Without Coarse Modulation) 254 Cycles
8× Interpolation (with or Without Coarse Modulation) 508 Cycles
Inverse Sinc (1× Interpolation) 10 Cycles
Inverse Sinc (2× Interpolation) 20 Cycles
Inverse Sinc (4× Interpolation) 40 Cycles
Inverse Sinc (8× Interpolation) 80 Cycles
Fine Modulation 12 Cycles
Power–Up Time 100 ms
Table 4. Maximum Rate
Maximum Rate (MSPS)
Interface Mode f
INTERFACE
f
DATA
f
HB1
f
HB2
f
HB3
f
DAC
Dual Port Mode 620 310 620 1000 1000 1000
Single Port Mode or Byte Mode 1200 300 600 1000 1000 1000
FIFO A
FIFO B
2×
2×
2×
CLK GENERATOR
AND DISTRIBUTOR
f
INTERFACE
f
DATA
f
HB1
f
HB2
f
HB3
f
DAC
DAC1
AND
DAC2
DAC3
AND
DAC4
32
32
32
DCIA
DACCLK
DATA
PORT A
DATA
PORT B
DATA
ASSEMBLER
INPUT
LATCH
DCIB
DATA
ASSEMBLER
INPUT
LATCH
R
E
A
D
P
T
R
A
R
E
A
D
P
T
R
B
WRITE PTR A
WRITE PTR B
32
32 32
INTERFACE
MODE
ONE DCI
DATAPATH
DATAPATH
2×
2×
2×
08910-003
Figure 3. Defining Maximum Rates