Datasheet

AD9148 Data Sheet
Rev. B | Page 68 of 72
EXAMPLE START-UP ROUTINE
To ensure reliable start-up of the AD9148, certain sequences
should be followed. An example start-up routine using the
following device configuration is used for this example.
• f
DATA
= 122.88 MSPS
• Interpolation = 4×, using HB1 = ’00’ and HB2 = ’000’
• Input data = baseband data
• Dual port mode with 1 DCI
• f
OUT
= 140 MHz
• f
REFCLK
= 122.88 MHz
• PLL = enabled
• Fine NCO = enabled
• Inverse sinc filter = disabled
• Synchronization = enabled
DERIVED PLL SETTINGS
The following PLL settings can be derived from the device
configuration:
• f
DACCLK
= f
DATA
× Interpolation = 491.52 MHz
• f
VCO
= 4 × f
DACCLK
= 1966.08 MHz (1 GHz < f
VCO
< 2 GHz)
• N1 = f
DACCLK
/f
REFCLK
= 4
• N0 = f
VCO
/f
DACCLK
= 4
DERIVED NCO SETTINGS
The following NCO settings can be derived from the device
configuration:
• f
OUT
= 140 MHz
• f
DACCLK
= f
DATA
× Interpolation = 491.52 MHz
• FTW = 140/(491.52) × 2
32
= 0x48, EAAAAA
START-UP SEQUENCE
The power clock and register write sequencing for reliable device
start-up follows:
• Power up the device (no specific power supply sequence is
required)
• Apply a stable REFCLK input signal.
• Apply a stable DCI input signal.
• Issue a hardware reset (optional)
• Configure device registers with the following write
sequence:
0x0C → 0xC9
0x0D → 0xD9
0x0A → 0xC0
0x0A → 0x80
0x10 → 0x48
0x14 → 0x40
0x17 → 0x08
0x17 → 0x00
0x19 → 0x08
0x19 → 0x00
0x1C → 0x40
0x1D → 0x00
0x1E → 0x01
0x54 → 0xAA
0x55 → 0xAA
0x56 → 0xEA
0x57 → 0x48
0x5A → 0x01
0x5A → 0x00
DEVICE VERIFICATION SEQUENCE
The following device polling can be conducted to verify that the
device is working properly:
• Read 0x06, Expect Bit 7 = 0, Bit 6 = 1, Bit 5 = 0, Bit 4 = 1,
Bit 2 = 1
• Read 0x12, Expect Bit 6 = 1
• Read 0x18, Expect 0x0F (0x07 is also normal)
• Read 0x1A, Expect 0x0F (0x07 is also normal)