Datasheet

AD9148 Data Sheet
Rev. B | Page 66 of 72
INTERRUPT REQUEST OPERATION
The AD9148 provides an interrupt request output signal
(Pin H4,
IRQ
) that can be used to notify an external host
processor of significant device events. Upon assertion of the
interrupt, the device should be queried to determine the precise
event that occurred. The
IRQ
pin is an open-drain, active low
output.
Pull the
IRQ
pin high external to the device. This pin may be
tied to the interrupt pins of other devices with open-drain outputs
to wired-OR these pins together.
Ten different event flags provide visibility into the device. These
10 flags are located in the two event flag registers (Register 0x06
and Register 0x07). The behavior of each of the event flags is
independently selected in the interrupt enable registers
(Register 0x04 and Register 0x05). When the flag interrupt
enable is active, the event flag latches and triggers an external
interrupt. When the flag interrupt is disabled, the event flag
simply monitors the source signal, and the external
IRQ
remains inactive.
Figure 91 shows the
IRQ
-related circuitry. Figure 91 shows how the
event flag signals propagate to the
IRQ
output. The interupt_enable
signal represents one bit from the interrupt enable register. The
event_flag signal represents one bit from the event flag register.
The event_flag_source signal represents one of the device signals
that can be monitored such as the PLL_locked signal from the
PLL phase detector or the FIFO Warning 1 signal from the
FIFO controller.
When an interrupt enable bit is set high, the corresponding event
flag bit reflects a positively tripped (that is, latched on the rising
edge of the event_flag_source version of the event_flag_source signal.
This signal also asserts the external
IRQ
. When an interrupt enable
bit is set low, the event flag bit reflects the current status of the
event_flag_source signal, and the event flag has no effect on the
external
IRQ
.
The latched version of an event flag (the interupt_source signal)
can be cleared in two ways. The recommended way is by writing 1
to the corresponding event flag bit. A hardware or software reset
also clears the interupt_source.
INTERRUPT SERVICE ROUTINE
Interrupt request management starts by selecting the set of event
flags that require host intervention or monitoring. Those events
that require host action should be enabled so that the host is
notified when they occur. For events requiring host intervention,
upon
IRQ
activation, run the following routine to clear an
interrupt request:
• Read the status of the event flag bits that are being
monitored.
• Set the interupt enable bit low so that the unlatched
event_flag_source can be monitored directly.
• Perform any actions that may be required to quiet the
event_source_flag. In many cases, no specific actions may
be required.
• Read the event flag to verify that the actions taken have
quieted the event_flag_source.
• Clear the interrupt by writing 1 to the event flag bit.
• Set the interrupt enable bits of the events to be monitored.
Noted that some of the event_flag_source signals are latched
signals. These are cleared by writing to the corresponding event
flag bit. Details of each of the event flags can be found in Table 12.
INTERRUPT_ENABLE
EVENT_FLAG_SOURCE
DEVICE_RESET
EVENT_FLAG
INTERRUPT
SOURCE
1
0
OTHER
INTERRUPT
SOURCES
IRQ
WRITE_1_TO_EVENT_FLAG
08910-088
Figure 91. Simplified Schematic of
IRQ
Circuitry