Datasheet

AD9148 Data Sheet
Rev. B | Page 6 of 72
INPUT/OUTPUT SIGNAL SPECIFICATIONS
T
MIN
to T
MAX
, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I
OUTFS
= 20 mA, maximum sample rate, unless
otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit
CMOS INPUT LOGIC LEVEL (SCLK, SDIO, CS, RESET, TMS, TDI, TCK)
Input V
IN
Logic High (IOVDD = 1.8 V) 1.2 V
Input V
IN
Logic High (IOVDD = 3.3 V) 2.0 V
Input V
IN
Logic Low (IOVDD = 1.8 V) 0.6 V
Input V
IN
Logic Low (IOVDD = 3.3 V) 0.8 V
CMOS OUTPUT LOGIC LEVEL (SDIO, SDO, IRQ, PLL_LOCK, TDO)
Output V
OUT
Logic High (IOVDD = 1.8 V) 1.4 V
Output V
OUT
Logic High (IOVDD = 3.3 V)
2.4
V
Output V
OUT
Logic Low (IOVDD = 1.8 V) 0.4 V
Output V
OUT
Logic Low (IOVDD = 3.3 V) 0.4 V
LVDS RECEIVER INPUTS (A[15:0]_x, B[15:0]_x, DCIA_x, DCIB_x)
Input Voltage Range, V
IA
or V
IB
825 1575 mV
Input Differential Threshold, V
IDTH
−100 +100 mV
Input Differential Hysteresis, V
IDTHH
to V
IDTHL
20 mV
Receiver Differential Input Impedance, R
IN
80 120 Ω
LVDS Input Rate, f
INTERFACE
(See Table 4) 1200 MSPS
LVDS RECEIVER INPUTS (FRAMEA_x, FRAMEB_x)
Input Voltage Range, V
IA
or V
IB
825 1575 mV
DAC CLOCK INPUT (CLK_P, CLK_N)
Differential Peak-to-Peak Voltage 100 500 2000 mV
Common-Mode Voltage (Self-Biasing, AC-Coupled) 1.25 V
Maximum Clock Rate
1000
MSPS
REFERENCE CLOCK INPUT (REFCLK_x/SYNC_x)
Differential Peak-to-Peak Voltage 100 500 2000 mV
Common-Mode Voltage (Self-Biasing, AC-Coupled)
1.25
V
Maximum Clock Rate 500 MSPS
Minimum Clock Rate (PLL Enabled)
Loop Divider = /2 125 MSPS
Loop Divider = /4 62.5 MSPS
Loop Divider = /8 31.25 MSPS
Loop Divider = /16 15.625 MSPS
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK) 40 MHz
Minimum Pulse Width High (t
PWH
) 12.5 ns
Minimum Pulse Width Low (t
PWL
) 12.5 ns
Set-Up Time, SDI to SCLK (t
DS
) 1.9 ns
Hold Time, SDI to SCLK (t
DH
) 0.2 ns
Data Valid, SDO to SCLK (t
DV
) 23 ns
Setup time, CS to SCLK (t
DCSB
)
1.4
ns