Datasheet

Data Sheet AD9148
Rev. B | Page 49 of 72
INTERFACE TIMING
The timing diagram for the digital interface port is shown in
Figure 59. The sampling point of the data bus nominally occurs
250 ps after each edge of the DCI signal and has an uncertainty of
± 250
ps when the DCI delay is set to 00b (Register 0x72[1:0]),
as illustrated by the sampling interval. The data and FRAME
signals must be valid throughout this sampling interval. The data
and FRAME signals may change at any time between sampling
intervals.
The setup (t
S
) and hold (t
H
) times with respect to the edges are
shown in Figure 59. The minimum setup and hold times are
shown in Table 16.
Table 16. Data Port Setup and Hold Times
DCI Delay
(Register 0x72, Bits[1:0])
Minimum Setup
Time, t
S
(ns)
Minimum Hold
Time, t
H
(ns)
00 −0.02 0.52
01 −0.16 0.78
10 −0.28 1.03
11 −0.36 1.16
The data interface timing can be verified by using the SED
circuitry. See the Interface Timing Validation section for details.
In data rate mode with synchronization enabled, a second timing
constraint between DCI and DACCLK must be met in addition
to the DCI-to-data timing shown in Table 17. In data rate mode,
only one FIFO slot is being used. The DCI to DACCLK timing
restriction is required to prevent data being written to and read
from the FIFO slot at the same time. The required timing
between DCI and DACCLK is shown in Figure 58.
DCI
DACCLK/
REFCLK
t
DATA
t
SDCI
t
HDCI
SAMPLING
INTERVAL
08910-057
Figure 58. Timing Diagram for Input Data Port (Data Rate Mode with Sync On)
Table 17. DCI to DACCLK Setup and Hold Times vs. DCI
Delay Value
DCI Delay
(Register 0x72,Bits[1:0])
Minimum Setup
Time, t
SDCI
(ns)
Minimum Hold
Time, t
HDCI
(ns)
00 −0.06 0.85
01 −0.22 1.14
10 −0.36 1.43
11 −0.45 1.59
t
DATA
t
S
t
H
SAMPLING
INTERVAL
DCI
DAT
A
SAMPLING
INTERVAL
08910-058
Figure 59. Timing Diagram for Input Data Ports