Datasheet

AD9148 Data Sheet
Rev. B | Page 42 of 72
FIFO OPERATION
DAC1
AND
DAC2
32
32 BITS
÷INT
DCIA
DCIB
DACCLK
DATA
PORT A
DATA
PORT B
DATA
PATHS
DATA
ASSEMBLER
INPUT
LATCH
DATA
ASSEMBLER
INPUT
LATCH
REG 0
REG 1
REG 2
REG 3
REG 4
REG 5
REG 6
REG 7
REG 0
REG 1
REG 2
REG 3
REG 4
REG 5
REG 6
REG 7
32
DAC3
AND
DAC4
3232
DATA
PATHS
32
WRITE PTR
RESET
WRITE PTR
RESET
READ
PTR
RESET
SYNC
LOGIC
FIFO RATE/
DATA RATE
FIFO A
OFS[2:0]
FIFO B OFS[2:0]
32 BITS
FRAMEB
FRAME
A
LOGIC
READ POINTER AREAD POINTER B
32
32
INTERFACE
MODE
ONE
DCI
WRITE PTR B
WRITE PTR A
08910-049
Figure 50. Block Diagram of FIFO
The AD9148 contains two 32-bit wide, 8-word deep FIFOs (one
per dual DAC) designed to relax the timing relationship between
the data arriving at the DAC input ports and the internal DAC
data rate clock. The FIFOs can also be used to provide an adjustable
pipeline delay between the DCIx clocks and the DACCLK allowing
realignment of data input in a multichip system. This significantly
increases the timing budget of the interface.
Figure 50 shows the block diagram of the datapath through the
FIFO. The data is latched into the device, is formatted, and is then
written into the FIFO register determined by the FIFO write
pointer. The value of the write pointer is incremented every time a
new word is loaded into the FIFO. Meanwhile, data is read from
the FIFO register determined by the read pointer and fed into
the digital datapath. The value of the read pointer is updated
every time data is read into the datapath from the FIFO. This
happens at the data rate, that is, the DACCLK rate divided by
the interpolation ratio. The difference between the write and
read pointers represents the FIFO pipeline delay and is
important to take into account when understanding the overall
pipeline delay of the AD9148.
In single-port and byte interface modes, the incoming digital data is
sampled at twice the data rate (DCIA). The data is then assembled
based on the interface mode. At the output of the data assembler
block, the data samples for DAC 1 and DAC 2 are written to FIFO A
and the data samples for DAC 3 and DAC 4 are written to FIFO B
at the data rate.
Valid data is transmitted through the FIFO as long as the FIFO
does not overflow or become empty. An overflow or empty
condition of the FIFO is the same as the write pointer and the
read pointer being equal. When both pointers are equal, an attempt
is made to read and write a single FIFO register simultaneously.
This simultaneous register access leads to unreliable data transfer
through the FIFO and must be avoided.