Datasheet

AD9148 Data Sheet
Rev. B | Page 4 of 72
FUNCTIONAL BLOCK DIAGRAM
FIFO
DATA RECEIVER
310MHz
310MHz
310MHz/620MHz 500MHz/1GHz 500MHz/1GHz
I OFFSET
Q OFFSET
f
S
/2
MOD
1.2GHz
1GHz
2× 2×
I GAIN
Q GAIN
2×
2×
2× 2×
FIFO
I OFFSET
COS
PHASE
CORRECTION
SIN
Q OFFSET
GAIN/
OFFSET_CTRL
SINC
–1
SINC
–1
SINC
–1
SINC
–1
2× 2×
I GAIN
Q GAIN
2×
2× 2×
INTERNAL CLOCK TIMING AND CONTROL LOGIC
2×
HB3_EN
HB3_CLK HB2_EN HB2_CLK HB1_EN HB1_CLK INVSINE_EN PREMOD_EN PREMOD_CLK MODE
SDO
SDIO
SCLK
CS
IRQ
RESET
FILTER
COEFFICIENT
16-BIT
DAC1
16-BIT
DAC2
32-BIT
NCO
16-BIT
DAC3
16-BIT
DAC4
GAIN
GAIN
AUX1
AUX2
GAIN
GAIN
AUX3
AUX4
DAC_CLK
SYNC
REFERENCE
BIAS
PLL_CTRL
CLOCK
MULTIPLIER
(2× – 16×)
MULTI-CHIP
SYNC
POWER-ON
RESET
SERIAL
IN/OUT PORT
PROGRAMMING
REGISTERS
FRAMEA_P/
FRAMEA_N
FRAMEB_P/
FRAMEB_N
DCIA_P/
DCIA_N
DCIB_P/
DCIB_N
B[15:0]_P/
B[15:0]_N
A[15:0]_P/
A[15:0]_N
16
16
IOUT1_P
IOUT1_N
AUX1_P
AUX1_N
IOUT2_P
IOUT2_N
AUX2_P
AUX2_N
IOUT3_P
IOUT3_N
AUX3_P
AUX3_N
IOUT4_P
IOUT4_N
AUX4_P
AUX4_N
VREF
I120
CLK_P
CLK_N
REFCLK_P/
SYNC_P
REFCLK_N/
SYNC_N
08910-002
f
S
/2
MOD
f
S
/2
MOD
f
S
/2
MOD
Figure 2.