Datasheet

AD9148 Data Sheet
Rev. B | Page 30 of 72
Register Name
Addr
(Hex) Bit Name Function Default
Sync Control 1 11 5:0 Sync phase request Offset of internal divided by 64 clock phase after sync. 000000
000000 = 0 DAC clocks.
…
111111 = 63 DAC clocks.
Sync Status 0
12
7
Sync Lost
Synchronization lost.
Read-
only
6 Sync locked Synchronization found.
Read-
only
Data Receiver Control 14 6 One DCI 0 = two DCIs used, DCIA_x and DCIB_x. 0
1 = one DCI used, DCIA_x.
Data Receiver Status 15 7
LVDS receiver
frame high
Frame input LVDS level > 1.7 V.
Read-
only
6
LVDS receiver
frame low
Frame input LVDS level < 0.7 V.
Read-
only
5
LVDS receiver
DCI high
DCI input LVDS level > 1.7 V.
Read-
only
4
LVDS receiver
DCI low
DCI input LVDS level < 0.7 V.
Read-
only
3
LVDS receiver
Port B high
Port B input LVDS level > 1.7 V.
Read-
only
2
LVDS receiver
Port B low
Port B input LVDS level < 0.7 V.
Read-
only
1
LVDS receiver
Port A high
Port A input LVDS level > 1.7 V.
Read-
only
0
LVDS receiver
Port A low
Port A input LVDS level < 0.7 V.
Read-
only
FIFO Status/
Control Port A
17
7
FIFO Warning 1
FIFO read and write pointers within ±1.
Read-
only
6 FIFO Warning 2 FIFO read and write pointers within ±2
Read-
only
5 FIFO reset aligned FIFO read and write pointers aligned after chip reset.
Read-
only
4
FIFO SPI align
acknowledge
FIFO read and write pointers aligned after SPI driven
FIFO reset.
Read-
only
3
FIFO SPI align
requesting
Request FIFO read and write pointers alignment via SPI. 0
2:0 FIFO phase offset
FIFO read and write pointer phase offset from optimal
phase following FIFO reset.
000
000 = 0 offset from optimal phase.
…
111 = 7 offset from optimal phase.
The optimal value is 0.